A New DSP Approach for 5G and AI Albert Camilleri VP Business Development North America VSORA Inc.
Company Background • Company founded in 2015 • Headquarters: France Paris • Each founder has more than 10 years experience in Digital Signal Tokyo San Diego Processor (DSP) design, working in global consumer markets Taipei Shenzhen • Previous founders’ designs widely used in successful consumer, automotive and industrial high volume products The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
Reinventing ‘Digital Signal Processing’ (DSP) 5G Wireless Communications • mmWave, MiMo, Beamforming, Carrier Aggregation Baseband • Enhanced 1Gbps+ Mobile Broadband Channel Wireless • Massive Machine Type Comms, Smart Home / Cities App RF Encoder DSP Processor Comms / • Ultra reliable low latency comms (< 1ms), IoT Decoder • New Short Range Wireless, 802.11af, ay, bb (LiFi) • Both terminals and infrastructure Artificial Intelligence (Terminals / Edge) DSP Artificial App Data • Neural Networks INFERENCE Intelligence Processor Result Trained Model • Image / video • Speech recognition / Audio • Language Translation The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
Traditional Architecture Limits Flexibility • Single threaded processors falling further behind 1 Gbps+ demand • Bespoke, fixed algorithm, co-processors increase the well known ASIC problems Host CPU Signals + In / Out Memory • Inflexible, hard to mature quickly, inappropriate in the new world of rapid standards evolutions The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
The Memory Bottleneck Problem Signal Memory bottleneck will stall and limit the promise of 5G and AI • Need for ever greater symbol word length and depth • Signal Memory (Cache) I/O bandwidth explosion • 5G modems and Massively Parallel Neural Network Processors are predominantly built on the same DSP type architectures today The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
Introducing the Matrix Processor Unit (MPU) VSORA MPU • Completely configurable: • Number of ALUs High BW Signal Memory • Memory size • Quantization (IEEE754 like), i.e. 3 1 2 4 number of exponent/mantissa bits Signals Manager Host • Liberates the “Bottleneck” Processor a1 b1 c1 a2 b2 c2 a3 b3 c3 a4 b4 c4 • Signal (cache) memory more tightly coupled ALUs + / x + / x + / x + / x • Signals manager pre-configures ACC ACC ACC ACC signal data • DSP is tightly controlled by the host processor The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
Single-core / Multi-core Architecture Completely configurable in terms of: • MPUs are programmed at an • The number of cores (single/multi-core) algorithm level in C++ with a MATLAB • The number of DMAs/core like API • High-level simulation methodology Multi-Core MPU provides performance/power/area trade-off data Vsora Vsora MPU-1 MPU-2 • Can be modified and iterated at Host CPU Signals + In / Out the algorithmic level to attempt Memory 100% DSP utilization Vsora Vsora • Algorithm code compiled directly MPU-4 MPU-3 to DSP via modified LLVM compiler • No low level code required • Engineering productivity enhancer Ability to map complex systems onto multiple cores, and dimension optimal solutions. The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
AI Supported Frameworks VSORA AI-DSP VSORA AI Framework Load Tool Graph Optimization High BW Signal Memory Model Quantization 3 1 2 4 Compiler Signals Manager a1 b1 c1 a2 b2 c2 a3 b3 c3 a4 b4 c4 ALUs + / x + / x + / x + / x VSORA Library ACC ACC ACC ACC The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
VSORA AI Solution • Fully programmable Solution • TensorFlow, PyTorch , …, supported frameworks • Configurable: • Number of MACs: 256, 1024, 2304, 4096, 6400, 9216, 12544, 16384, …, 65536 • IEEE754 Quantization: number of bits (sign/exponent/mantissa) • Number of DMAs • High MPU processing efficiency • Does not suffer memory bandwidth bottleneck to load large numbers of MACs The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
Reinvented Development Flow ASIC Hardware Integration Algorithm Implementation Signal Processing High-Level Code • Wired logic Definition Related HW or Specifications (DSP Co-Pro) • DSP HW Engineers Drawbacks [Verilog, System Verilog] months • Four different, large engineering teams Link Layer Software • Very slow process , exceedingly expensive Development Binary Code Algorithms Rework Algo Engineers DSP Engineers API Definition Required [MATLAB] [C/C++/Verilog/VHDL] SW Engineers [C/C++] ASIC Hardware Integration Algorithms definition MSP Benefits Configuration • Reduced personnel min HW Engineers • Fast algorithm definition and DSP MSP dimensioning Link Layer Software [Verilog, System Verilog] Development dimensioning High Level Code • Easy integration of Signal Processing & Algo Engineers [MATLAB Like] SW Engineers Embedded SW code [C/C++] Simulation Platform The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
Summary Highly configurable “tiled” solution • “Unlimited” number of Cores • Scalable memory/DMA bandwidth avoids bottlenecks Eliminates need for inflexible co-processors • Flexible coding: mix signal processing and link-layer/neural-processing SW Implementation independent, high-level programmability • Supports design flexibility to facilitate market evolution Tiered simulation platforms • MATLAB/Tensorflow level, FPGA (Cloud) platform, IP/RTL simulation Compiler technology empowers 100% DSP utilization • Optimizes engineering efficiency • Facilitates performance/area/power tradeoffs The information contained in this document is confidential and shall not be disclosed to third parties without a written consent from Vsora
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