Final Workshop of CDC 2002-2007 Tallinn, Brotherhood of the Blackheads, 21 – 22 January 2008 A multi- -layer layer A multi A multi-layer research and training platform research and training platform research and training platform for system- -on on- -chip testing: chip testing: for system for system-on-chip testing: Hardware, Software and Web Interface Hardware, Software and Web Interface Hardware, Software and Web Interface Artur ur Jutman Jutman an Artur ur an Department of Computer Engineering Dept. of Computer Engineering Tallinn University of Technology Tallinn University of Technology Estonia Estonia
A multi-layer research and training platform for system-on-chip testing Outline � Introduction and motivation � Different layers of the platform � HW tools � PC-based tools � Web interface � E-Learning tools � Conclusions and discussion 2
A multi-layer research and training platform for system-on-chip testing Motivation � Cutting Edge Research − Needs custom developed algorithms and/or tools � PhD Students − Need to run their experiments � Undergraduate Students − Need introduction to the topic � Department − Needs training materials and research 3
A multi-layer research and training platform for system-on-chip testing Different layers of the platform Web Tools PC Tools Hardware Tools 4
A multi-layer research and training platform for system-on-chip testing Main components of the platform � DefSim - an integrated measurement environment for physical defect study in CMOS circuits. � TurboTester – a research and training toolkit with extensive set of tools for digital test and design for testability � Web-based runtime interface for remote access to our tools � Java applets – illustrative e-learning software written specifically for the web � Other tools 5
A multi-layer research and training platform for system-on-chip testing Different layers of the platform Web Tools PC Tools Hardware Tools 6
A multi-layer research and training platform for system-on-chip testing Defect Study using DefSim � DefSim is an integrated circuit (ASIC) and a measurement equipmrnt for experimental study of CMOS defects. � The central element of the DefSim equipment is an educational IC with a large variety of shorts and opens physically inserted into a set of simple digital circuits. � The IC is attached to a dedicated measurement box serving as an interface to the computer. The box supports two measurement modes - voltage and I DDQ testing. http://www.defsim.com 7
A multi-layer research and training platform for system-on-chip testing DefSim IC details − Standard industrial CMOS technology − Area 19.90 mm 2 − Approx. 48000 transistors − 62 pins − JLCC68 package A built- -in current monitor in current monitor A built for I I DDQ testing is is for DDQ testing implemented in each block. implemented in each block. 8
A multi-layer research and training platform for system-on-chip testing Implementation of defects NAND2 cell with floating gate NAND2 cell with floating gate VDD Q X A B GND 9
A multi-layer research and training platform for system-on-chip testing Implementation of defects NAND2 cell with D- -S short (missing poly) S short (missing poly) NAND2 cell with D VDD Q A B • Altogether there are over 500 different defects on the chip • Implemented defects are shorts GND and opens in metal and poly layers • To be close to the silicon reality each cell is loaded and driven by standard non-inverting buffers 10
A multi-layer research and training platform for system-on-chip testing DefSim in the classroom � With DefSim you can � Observe the truth table of correct circuit � Observe the truth table of defective circuit � Obtain defect/fault tables for all specific defects � Define test patterns automatically or manually � Activate IDDQ and voltage measurements � Study behavior of bridging and open faults � Study and compare different fault models 11
A multi-layer research and training platform for system-on-chip testing DefSim lab environment “Plug and Play” – dedicated hardware and software 12
A multi-layer research and training platform for system-on-chip testing DefSim user interface 13
A multi-layer research and training platform for system-on-chip testing Different layers of the platform Web Tools PC Tools Hardware Tools 14
A multi-layer research and training platform for system-on-chip testing PC-Based Toolkit – Turbo Tester Algorithms: Deterministic Levels: Circuits: Formats: Random Gate Combinational Hazard EDIF Genetic Multivalued Macro Sequential Analysis AGM RTL Simulator Data Logic Test Simulator Generators Specifi- Test Design cation Defect Set Fault BIST Library Simulator Emulator Methods: Fault models: Faulty Design Error Test Set BILBO Fault Stuck-at faults Area Diagnosis Optimizer CSTP Table Physical defects Hybrid Used in 100+ institutions in 47 countries http://www.pld.ttu.ee/tt 15
A multi-layer research and training platform for system-on-chip testing Turbo Tester’s user interface http://www.pld.ttu.ee/tt 16
A multi-layer research and training platform for system-on-chip testing Turbo Tester: Basic Facts Freeware � Freeware � Downloadable via the Web � Downloadable via the Web � Windows, Linux, UNIX/Solaris � Windows, Linux, UNIX/Solaris � EDIF design interface � EDIF design interface � ATPGs, BIST, simulators, test , BIST, simulators, test � ATPGs � compaction compaction Provides homogeneous environment � Provides homogeneous environment � for research and training for research and training 17
A multi-layer research and training platform for system-on-chip testing Different layers of the platform Web Tools PC Tools Hardware Tools 18
A multi-layer research and training platform for system-on-chip testing BIST Analyzer: covered topics � Test Pattern Generators (PRPG): − LFSR Typical BIST Architecture − Modular LFSR BIST Test Pattern − Cellular Automata Control Generator − GLFSR Unit (PRPG) ........ − Weighted TPG − etc. � Combined Techniques BIST Circuit Under (PRPG + Memory): Test (CUT) Memory − Reseeding − Multiple polynomial BIST ........ − Hybrid BIST − Bit-Flipping BIST Output Response − Column matching BIST Analyzer (MISR) − etc. 19
A multi-layer research and training platform for system-on-chip testing BIST Analyzer: covered topics • Different embedded generators (PRPG) and their properties • PRPG optimization methodologies and algorithms • Mixed-mode BIST solutions (PRPG+memory) • Fault detection and diagnosis in BIST 20
A multi-layer research and training platform for system-on-chip testing BIST Analyzer 21
A multi-layer research and training platform for system-on-chip testing Different layers of the platform Web Tools PC Tools Hardware Tools 22
A multi-layer research and training platform for system-on-chip testing Web Interface 23
A multi-layer research and training platform for system-on-chip testing Different layers of the platform Web Tools PC Tools Hardware Tools 24
A multi-layer research and training platform for system-on-chip testing E-Learning software on DFT http://www.pld.ttu.ee/applets 25
A multi-layer research and training platform for system-on-chip testing Benefits of e-learning software � Essential supplement to the university lectures � Accessibility over Internet � Visual content � Comprehensive examples � Better organization of teaching materials � Based on free educational software � Distance learning & computer aided teaching � Easy to implement in other universities � Constantly updated 26
A multi-layer research and training platform for system-on-chip testing E-Learning Software Turbo Java Tester Applets Web based tools for classroom, home and exams Learning Tools for laboratory research Scenario 1 Scenario 1 Scenario 2 Scenario 2 Scenario 3 Scenario 3 Scenario 4 Test Scenario 4 Test Scenarios Error Error Built- Built -In In Generation Generation Design for Design for Diagnosis Diagnosis Self- -Test Test Self Testability Testability Test Design for Turbo Supporting Scenario 1 Scenario 1 Scenario 2 Scenario 2 Generation Testability Scenario 3 Scenario 3 Tester Scenario 4 Scenario 4 Test Test Materials Error Error Built- Built -In In Generation Design for Generation Design for Diagnosis Diagnosis Self Self- -Test Test Testability Testability Error Built-In Diagnosis Self-Test Test and Diagnostics Applet on Basics Schematic of Test & & DD Editor Diagnostics RTL Design and Test Applet on RTL Design and Test Group of Applet on Boundary Applets on FSM Boundary Scan Scan Decomposition Standard 27
A multi-layer research and training platform for system-on-chip testing E-Learning Software Software for classroom, home, labs and exams: Logic level diagnostics System level test & DfT Boundary Scan http://www.pld.ttu.ee/applets 28
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