A Design Flow and Evaluation Framework for DPA-resistant Instruction - PowerPoint PPT Presentation

A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions Francesco Regazzoni 1,4 , Alessandro Cevrero 2,3 , François-Xavier Standaert 1 , Stephane Badel 3 , Theo Kluter 2 , Philip Brisk 2 , Yusuf Leblebici 3 , and Paolo Ienne 2 Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 1 1 UCL Crypto Group, Université catholique de Louvain, Louvain-la-Neuve, Belgium. 2 School of Computer and Communication Sciences - EPFL, Lausanne, Switzerland. 3 School of Engineering - EPFL, Lausanne, Switzerland. 4 ALaRI - University of Lugano, Lugano, Switzerland.

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 2 ISE ISE ISE ALU Memory

A Motivating Example Register File IMM. B A Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 3 ISE ISE ISE ALU Memory

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 4 ISE ISE ISE ALU Memory

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 5 ISE ISE ISE ALU Memory

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 6 ISE ISE ISE ALU Memory

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 7 ISE ISE ISE ALU Memory

A Motivating Example Something easier? Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 8

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 9 ISE ISE ISE ALU Memory

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 10 ISE ISE ISE ALU Memory

A Motivating Example Register File IMM. A B Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 11 ISE ISE ISE ALU Memory

Contributions and Goals Bring a security metric to the forefront of design variables to be optimized Create an automated design flow for combining protected and non protected logic styles Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 12 Explore type and amount of protected circuit vs level of security trade offs

Needed �Bri ks� Tool for extracting ISE... Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Protected logic and its design flow... Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Protected logic and its design flow... � Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Protected logic and its design flow... � Simulation environment... Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Protected logic and its design flow... � Simulation environment... � Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Protected logic and its design flow... � Simulation environment... � Sp eak er: Metric... F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Protected logic and its design flow... � Simulation environment... � Sp eak er: Metric... � F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13

Needed �Bri ks� Tool for extracting ISE... � Main question Protected logic and its design flow... � Simulation environment... � Sp eak er: Metric... � F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 13 Can I really plug all the bricks together and obtain something meaningful?

Outline 1 What we put together 2 Validation of our design flow 3 Results and comments Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 14

The CMOS Design Flo w software processor HDL code crypto.c Protected ISE HDL code Library Protected ISE Extractor Synth and P&R CMOS Library CMOS Synth and Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 15 P&R crypto_ISE.c 0101001. 0101001. 1100001. SPICE level 1100001. simulation Security Evaluaton

The Pro esso r Customization software processor HDL code crypto.c Protected ISE HDL code Library Protected ISE Extractor Synth and P&R CMOS Library CMOS Synth and Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 16 P&R crypto_ISE.c 0101001. 0101001. 1100001. SPICE level 1100001. simulation Security Evaluaton

The Prote ted Design Flo w software processor HDL code crypto.c Protected ISE HDL code Library Protected ISE Extractor Synth and P&R CMOS Library CMOS Synth and Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 17 P&R crypto_ISE.c 0101001. 0101001. 1100001. SPICE level 1100001. simulation Security Evaluaton

The Hyb rid Design Flo w software processor HDL code crypto.c Protected ISE HDL code Library Protected ISE Extractor Synth and P&R CMOS Library CMOS Synth and Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 18 P&R crypto_ISE.c 0101001. 0101001. 1100001. SPICE level 1100001. simulation Security Evaluaton

The Simulation Environment software processor HDL code crypto.c Protected ISE HDL code Library Protected ISE Extractor Synth and P&R CMOS Library CMOS Synth and Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 19 P&R crypto_ISE.c 0101001. 0101001. 1100001. SPICE level 1100001. simulation Security Evaluaton

The Design Evaluation software processor HDL code crypto.c Protected ISE HDL code Library Protected ISE Extractor Synth and P&R CMOS Library CMOS Synth and Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 20 P&R crypto_ISE.c 0101001. 0101001. 1100001. SPICE level 1100001. simulation Security Evaluaton

Outline 1 What we put together 2 Validation of our design flow 3 Results and comments Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 21

F eatures of Op enRISC OpenRISC 1000 ISA 32 bit 5 stages pipeline Sp eak er: ISE support F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 22 100 MHz Compiler: cross-compiler gcc 3.4.4

F eatures of CMOS and MCML CMOS target library: commercial 0.18 µ m Protected logic: MOS Current Mode Logic (MCML) ◮ Standard cell Library (roughly 150 gates) Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 23 ◮ High speed, fully differential, almost constant power consumption ◮ Differential routing (wire pairs along the same path) ◮ Fully automated design flow

F eatures of Info rmation Theo ry Metri Measures asymptotic resistance against the strongest attacker Independent from the DPA scenario Overcomes limitations of specific leakage models Sp eak er: F ran es o Regazzoni Design Flo w and Evaluation F ramew o rk fo r DP A-resistant ISE P . 24 Main Steps: ◮ Inputs: power consumption trace, secret key ◮ Add white noise ◮ Reduce the dimension using PCA ◮ Compute the mutual information