45nm High-k + Metal Gate Strain-Enhanced Transistors C. Auth, A. - PowerPoint PPT Presentation

45nm High-k + Metal Gate Strain-Enhanced Transistors C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren%, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, C. Wiegand Portland Technology Development, % PTM Intel Corporation 1

Outline • Introduction • Metal-Gate + Strain Integration • Transistor/Circuit Results • Manufacturing • Conclusions 2

Introduction • SiON scaling running out of atoms • Poly depletion limits inversion T OX scaling – > Need High-K + Metal Gate 10 1000 Electrical (Inv) Tox (nm) Poly Gate Leakage (Rel.) 100 SiON Silicon 10 1 0.1 1 0.01 350nm 250nm 180nm 130nm 90nm 65nm 3

High-k + Metal Gate Benefits • High-k gate dielectric – Reduced gate leakage – T OX scaling • Metal gates – Eliminate polysilicon depletion – Resolves V T pinning and poor mobility for high-k gate dielectrics 4

Metal Gate Flow Options Gate-First Dep Hi-k & Patt Met 1 & Patt Met 2 & S/D formation & Met 1 Dep Met 2 Etch Gates Contacts Hik-First, Gate-Last Dep & Patt S/D formation & Rem Gate & Dep Met 2+Fill & Hik+Gate ILD dep/polish Patt Met 1 Polish 5

Metal Gate-Last Benefits • High Thermal budget available for Midsection – Better Activation of S/D Implants • Low thermal budget for Metal Gate – Large range of Gate Materials available • Significant enhancement of strain – Both NMOS and PMOS benefits • Low cost – Total wafer cost adder - 4% 6

Outline • Introduction • Metal-Gate + Strain Integration • Transistor/Circuit Results • Manufacturing • Conclusions 7

Methods of NMOS Strain at 65nm • Tensile Nitride Cap • Stress Memorization → Gate + S/D 8

Methods of NMOS Strain at 65nm • Tensile Nitride Cap • Stress Memorization → Gate + S/D 9

NMOS strain: Tensile Cap Layer • Running out of space for Nitride Cap Layer – Pitch degradation increases with pinchoff of film – Requires higher stress & thinner films 13 Idsat % gain 11 9 7 5 300 250 200 150 100 Pitch (nm) 10

Tensile Contact Stress • Use Tensile trench contacts to stress channel Trench Contacts Poly 11

Tensile Contact Stress • Use of Tensile trench contacts provide 10% Idsat improvement • Matched Contact Resistance 1000 VDD = 1.0V Ioff (nA/  m) 100 +10% 10 Tensile Fill Control 1 0.70 0.90 1.10 1.30 Idsat (mA/  m) 12

NMOS strain: Metal Gate Stress • Gate Stress Memorization incompatible with Gate- Last • Compressive Gate fill material induces strain directly* – *C. Kang, et al, IEDM 2006 Compressive Gate Fill 45nm 65nm 13

Compressive Gate Stress • Compressive Gate Fill shows 5% Idsat improvement • Additive with Tensile Trench contacts 1000 VDD = 1.0V Ioff (nA/  m) 100 +5% 10 Compressive Gate Control 1 0.9 1.1 1.3 1.5 Idsat (mA/  m) 14

Mitigation of NMOS stress on PMOS • Tensile Contact fill mitigated by raised SiGe S/D • Metal Gate Strain compensated by PMOS WFM Raised S/D Different gate stack NMOS PMOS 15

Gate Fill scalability for Gate-Last • Capability to <30nm demonstrated 2.0 Normalized sheet rho P-type gate 1.5 N-type gate 1.0 30nm 0.5 20 30 40 50 60 Gate Length (nm) 16

PMOS strain: Pitch dependence • Embedded SiGe S/D mobility enhancement strongly dependent on pitch 1.4 1.3 Normalized Idsat Pitch 1.2 scaling 1.1 1.0 0.9 0.8 65nm 45nm Technology node 17

Embedded SiGe S/D 65nm • Continued Scaling for SiGe S/D 1. Ge concentration inc. to 30% 2. Gate → S/D distance reduced Gate-to-SiGe S/D (nm) 35 40 45nm Ge Conc. (%) 30 25 20 10 15 0 90nm 65nm 45nm Technology node 18

PMOS Strain: Gate-Last Flow • Use of Gate-Last Flow enhances Embedded SiGe S/D* – *J. Wang, et al, VLSI 2007 • Removal of poly gate increases channel stress by 50% Before gate removal After gate removal 19

PMOS Strain Components • Three methods used enhance PMOS performance 1. Increase Ge Concentration in Embedded SiGe S/D 2. Move Embedded SiGe S/D closer to Gate 3. Remove dummy poly gate with Metal Gate-Last flow Remove Gate Move SiGe Increase %Ge ↑ 20

PMOS strain: Pitch dependence • Stress degraded due to Pitch Scaling 1.4 1.3 Normalized Idsat Pitch 1.2 scaling 1.1 1.0 0.9 0.8 65nm 45nm Technology node 21

PMOS strain: Pitch dependence • Proximity scaling recovers majority of pitch degradation 1.4 1.3 Normalized Idsat 1.2 Proximity 1.1 Reduction 1.0 0.9 0.8 65nm 45nm Technology node 22

PMOS strain: Pitch dependence • %Ge provides strain benefit 1.4 1.3 Normalized Idsat Increase to 30% Ge 1.2 1.1 1.0 0.9 0.8 65nm 45nm Technology node 23

PMOS strain: Pitch dependence • Gate-Last provides significant increase in performance Removal of 1.4 Gate 1.3 Normalized Idsat 1.2 1.1 1.0 0.9 0.8 65nm 45nm Technology node 24

Strain Comparison 65nm Method 45nm Method NMOS NMOS Tensile Nitride Cap Tensile Trench Contacts Gate Stress Memorization + Metal Gate Stress (MGS) S/D Stress Memorization + S/D Stress Memorization PMOS PMOS Embedded SiGe S/D Embedded SiGe S/D (higher %Ge + reduced S/D) Replacement Gate Enhancement 25

Outline • Introduction • Metal-Gate + Strain Integration • Transistor/Circuit Results • Manufacturing • Conclusions 26

Gate Leakage • Gate leakage is reduced >25X for NMOS and 1000X for PMOS 100 SiON/Poly 65nm Normalized Gate Leakage 10 1 SiON/Poly 65nm 0.1 0.01 0.001 HiK+MG 45nm HiK+MG 45nm 0.0001 NMOS PMOS 0.00001 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 VGS (V) 65nm: Bai, 2004 IEDM 27

Excellent short channel effects • Subthreshold slope - 100mV/decade • DIBL - 140mV/V NMOS & 200mV/V PMOS 10000 PMOS NMOS 1000 100 Id (  A/  m) 10 1 0.1 |Vds|=1.0V 0.01 |Vds|=0.05V 0.001 0.0001 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 Vgs (V) 28

NMOS I DSAT vs. I OFF • Best drives for 45nm or 32nm technology 1000 VDD = 1.0V 12% Ioffn (nA/  m) 100 65nm [Tyagi, 2005 IEDM] 160 nm 10 1 0.8 1.0 1.2 1.4 1.6 Idsatn (mA/  m) 1.36 mA/  m at I OFF = 100 nA/  m & 1.0V 12% better than 65 nm 29

NMOS I Dlin vs. I OFF 1000 VDS = 0.05V 8% Ioff (nA/  m) 100 65nm [Tyagi, 2005 IEDM] 160 nm 10 1 0.13 0.15 0.17 0.19 0.21 Idlin (mA/  m) 0.192 mA/  m at I OFF = 100 nA/  m 8% better than 65 nm 30

PMOS I DSAT vs. I OFF • Best drives for 45nm or 32nm technology 1000 VDD = 1.0V 65nm [Tyagi, 2005 IEDM] Ioffp (nA/  m) 100 51% 160 nm 10 1 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Idsatp (mA/  m) 1.07 mA/  m at I OFF = 100 nA/  m & 1.0V 31 51% better than 65nm

PMOS I Dlin vs. I OFF VDS = 0.05V 1000 72% Ioff (nA/  m) 100 160 nm 10 65nm [Tyagi, 2005 IEDM] 1 0.08 0.11 0.14 0.17 0.2 Idlin (mA/  m) 0.178 mA/  m at I OFF = 100 nA/  m 72% better than 65nm! 7% from NMOS 32

SOC Application • LSTP benchmark (1nA & 1.1V) 100 100 65nm @ 1.2V 65nm @ 1.2V [Post, 2006 IEDM] [Post, 2006 IEDM] Ioffp (nA/  m) 10 10 Ioffn (nA/  m) 1 1 0.1 0.1 0.01 0.01 0.2 0.4 0.6 0.8 1.0 1.2 0.4 0.6 0.8 1.0 1.2 1.4 Idsatn (mA/  m) Idsatp (mA/  m) NMOS: 1.04 mA/  m at I OFF = 1 nA/  m & 1.1V PMOS: 0.88 mA/  m at I OFF = 1 nA/  m & 1.1V 33

Ring Oscillator Speed Component Component Benefit Benefit 9 (%) (%) FO=2 D E LA Y P E R S TA GE (pS ) PMOS Idsat PMOS Idsat +13 +13 8 65nm @ 1.2V PMOS Idlin PMOS Idlin +18 +18 7 NMOS Idsat NMOS Idsat +3 +3 6 NMOS Idlin NMOS Idlin +2 +2 5 Cjunction Cjunction +2 +2 4 45nm @1.1V Cgate/Cov Cgate/Cov -8 -8 3 Voltage Scaling Voltage Scaling -7 -7 10 100 1000 10000 IOFFN + IOFFP (nA/um) Total Total +23 +23 Metal Gate Last flow enables 23% reduction in RO delay at the same leakage 34

Power: SRAM VCCmin • Low active VCCmin important for low power applications • 3Mb SRAM – 0.346  m 2 cell median active VCCmin of 0.70V – 0.382  m 2 cell median active VCCmin of 0.625V 35

Outline • Introduction • Metal-Gate + Strain Integration • Transistor/Circuit Results • Manufacturing • Conclusions 36

193nm Dry lithography - Poly • Critical Layers patterned with 193nm Dry lithography – Lower cost & Mature toolset – Transistor Formation Mask Count Neutral with 65nm • Double Patterning used at Poly Poly – Array of Poly lines are patterned – Discrete allowed pitches Post 1 st layer – Poly lines are Cut Cuts Post 2 nd layer 65nm SRAM 45nm SRAM 37

Multiple Microprocessors Single Core Dual Core Quad Core Six Core 38

Defect Reduction Trend • Record yields demonstrated <2 years after 65 nm – Fastest Ramp to high yield ever at Intel 90 nm 65 nm 45 nm Defect Density 2yrs (log scale) 2001 2002 2003 2004 2005 2006 2007 2008 2009 39