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3D Packaging Structure for High Temperature Power electronics Raphal - PowerPoint PPT Presentation

3D Packaging Structure for High Temperature Power electronics Raphal R IVA 1 , Cyril B UTTAY 1 , Rmi P ERRIN 1 , Marie-Laure L OCATELLI 2 , Vincent B LEY 2 , Bruno A LLARD 1 1 Laboratoire Ampre, Lyon, France 2 Laboratoire LAPLACE, Toulouse,


  1. 3D Packaging Structure for High Temperature Power electronics Raphaël R IVA 1 , Cyril B UTTAY 1 , Rémi P ERRIN 1 , Marie-Laure L OCATELLI 2 , Vincent B LEY 2 , Bruno A LLARD 1 1 Laboratoire Ampère, Lyon, France 2 Laboratoire LAPLACE, Toulouse, France 16/10/14 1 / 25

  2. Outline Introduction The 3-D structure Module Manufacturing Conclusion 2 / 25

  3. Outline Introduction The 3-D structure Module Manufacturing Conclusion 3 / 25

  4. High Temperature Power Electronics ◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225° C) ◮ Long operating life (up to 30 years) 4 / 25

  5. High Temperature Power Electronics ◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225° C) ◮ Long operating life (up to 30 years) ◮ Share the cooling system between electrical and internal combustion engines. ◮ Cooling fluid temperature: 120 ° C 4 / 25

  6. High Temperature Power Electronics ◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225° C) ◮ Long operating life (up to 30 years) ◮ Share the cooling system between electrical and internal combustion engines. ◮ Cooling fluid temperature: 120 ° C ◮ continuous operation, low thermal cycles count ◮ e.g 5 years operation at 225° C 4 / 25

  7. High Temperature Power Electronics ◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225° C) ◮ Long operating life (up to 30 years) ◮ Share the cooling system between electrical and internal combustion engines. ◮ Cooling fluid temperature: 120 ° C ◮ continuous operation, low thermal cycles count ◮ e.g 5 years operation at 225° C ◮ Nasa mission to Venus: up to 480° C ◮ Mission to Jupiter: 100 bars, 400° C 4 / 25

  8. Active Power Devices for High Temperature Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013 250 -50 ◦ C -10 ◦ C 27 ◦ C 70 ◦ C 107 ◦ C 70 310°C 200 60 160 ◦ C 150 Drain current [A] 50 196 ◦ C V out [V] 40 234 ◦ C 100 270 ◦ C 30 50 20 0 10 50 0 49.0 48.8 48.6 48.4 0.2 0.0 0.2 0 2 4 6 8 10 12 time [ µ s] time [ µ s] Drain-to-Source voltage [V] Previous results: SiC JFETs are attractive for > 200 ° C operation: ◮ rated at 1200 V (or more), several Amps ◮ Voltage-controlled devices ◮ No reliability issue related to gate oxide degradation 5 / 25

  9. High Temperature Thermal Management Buttay et al. “Thermal Stability of Silicon Carbide Power JFETs”, IEEE Trans on Electron Devices, 2014 80 70 SiC JFET: Run-away 60 ◮ 490 m Ω , 1200 V power [W] ◮ R Th JA = 4 . 5 K / W 50 ◮ 135 ° C ambient ◮ On-state losses 40 current changed from 3.65 to 3.7 A 30 100 150 200 250 300 350 time [s] High temperature capability � = reduced cooling needs! SiC JFETs must be attached to a low- R Th cooling system. 6 / 25

  10. Double Side Cooling ◮ Standard packaging offers cooling through one side of the die only ◮ “3-D” or “Sandwich” package: thermal management on both sides ◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact 7 / 25

  11. Double Side Cooling ◮ Standard packaging offers cooling through one side of the die only ◮ “3-D” or “Sandwich” package: thermal management on both sides ◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact 7 / 25

  12. Outline Introduction The 3-D structure Module Manufacturing Conclusion 8 / 25

  13. The proposed 3-D Structure V bus J H OUT J L GND ◮ Two ceramic substrates, in “sandwich” configuration ◮ Two SiC JFET dies (SiCED) ◮ assembled using silver sintering ◮ 25.4 mm × 12.7 mm (1 in × 0.5 in) 9 / 25

  14. Ceramic Substrates Copper Alumina ◮ Si 3 N 4 identified previously for 0.16 mm high temperature 0.15 mm 0,15 mm Source Gate Source 0,3 mm ◮ For development: use of 0.2 mm alumina SiC JFET ◮ Etching accuracy exceeds 0.3 mm Drain standard design rules ◮ Double-step copper etching for die contact ➜ Custom etching technique Scale drawing for 2.4 × 2.4 mm 2 die 10 / 25

  15. Bonding Material: Silver Sintering Silver Paste ◮ Based on micro-scale silver particles (Heraeus LTS-117O2P2) ◮ Low temperature (240 ° C) sintering Göbl, C. et al “Low temperature sinter technology Die attachment for automotive ◮ Low pressure (2 MPa) process power electronic applications” proc of APE, 2006 No liquid phase involved: ◮ No movement of the die ◮ No bridging across terminals ◮ No height compensation thanks to wetting 11 / 25

  16. 3-D Structure: Challenges ◮ Behaviour of silver paste during assembly (bridging, compensation of height differences) ◮ High-resolution alignment of parts ◮ Etching resolution of the DBC substrates 12 / 25

  17. 3-D Structure: Challenges ◮ Behaviour of silver paste during assembly (bridging, compensation of height differences) ◮ High-resolution alignment of parts ◮ Etching resolution of the DBC substrates 12 / 25

  18. 3-D Structure: Challenges ◮ Behaviour of silver paste during assembly (bridging, compensation of height differences) ◮ High-resolution alignment of parts ◮ Etching resolution of the DBC substrates 12 / 25

  19. Outline Introduction The 3-D structure Module Manufacturing Conclusion 13 / 25

  20. Preparation of the Substrates plain DBC board 14 / 25

  21. Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 14 / 25

  22. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and coating Development 14 / 25

  23. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching coating Development 14 / 25

  24. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching coating Development 14 / 25

  25. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching 3a - resin coating coating Development 14 / 25

  26. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching 3a - resin coating coating Development 3b - Exposure and Developpment 14 / 25

  27. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching 3a - resin coating coating Development 4a - Photosentive fi lm 3b - Exposure and laminating Developpment 14 / 25

  28. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching 3a - resin coating coating Development 4b - Exposure and 4a - Photosentive fi lm 3b - Exposure and Development laminating Developpment 14 / 25

  29. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching 3a - resin coating coating Development 5 - Etching 4b - Exposure and 4a - Photosentive fi lm 3b - Exposure and Development laminating Developpment 14 / 25

  30. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching 3a - resin coating coating Development 5 - Etching 4b - Exposure and 4a - Photosentive fi lm 3b - Exposure and Development laminating Developpment 14 / 25

  31. Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching 3a - resin coating coating Development 6 - Singulating 5 - Etching 4b - Exposure and 4a - Photosentive fi lm 3b - Exposure and Development laminating Developpment 14 / 25

  32. Preparation of the Substrates ◮ Final patterns within 50 µ m of desired size ◮ Two designs, for 2.4 × 2.4 mm 2 and 4 × 4 mm 2 dies ◮ Total copper thickness 300 µ m, ≈ 150 µ m per step 14 / 25

  33. Preparation of the Dies ◮ Standard aluminium topside finish not compatible with silver sintering Die Mask ◮ Ti/Ag PVD on contact areas PVD ◮ Need for a masking solution ➜ jig with locating pockets. 15 / 25

  34. Preparation of the Dies ◮ Standard aluminium topside finish not compatible with silver sintering Die Mask ◮ Ti/Ag PVD on contact areas PVD ◮ Need for a masking solution ➜ jig with locating pockets. Before PVD 15 / 25

  35. Preparation of the Dies ◮ Standard aluminium topside finish not compatible with silver sintering Die Mask ◮ Ti/Ag PVD on contact areas PVD ◮ Need for a masking solution ➜ jig with locating pockets. Before PVD After Ti/Ag PVD 15 / 25

  36. Sintering process assembly without drying ◮ 30 min Drying step at 85 ° C, 30 min sintering at 240 ° C. ◮ 5 minutes pre-drying before assembly, to increase paste viscosity ◮ use of a glass die to observe paste spreading ◮ Sintering under low pressure (2 MPa) 16 / 25

  37. Sintering process assembly without drying 5 min pre-drying ◮ 30 min Drying step at 85 ° C, 30 min sintering at 240 ° C. ◮ 5 minutes pre-drying before assembly, to increase paste viscosity ◮ use of a glass die to observe paste spreading ◮ Sintering under low pressure (2 MPa) 16 / 25

  38. Sintering process assembly without drying 5 min pre-drying ◮ 30 min Drying step at 85 ° C, 30 min sintering at 240 ° C. ◮ 5 minutes pre-drying before assembly, to increase paste viscosity ◮ use of a glass die to observe paste spreading ◮ Sintering under low pressure (2 MPa) 16 / 25

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