High Temperature, Smart Power Module for Aircraft Actuators Khalil E L F ALAHI , Stanislas H ASCOËT , Cyril B UTTAY , Pascal B EVILACQUA , Luong-Viet P HUNG , Dominique T OURNIER , Bruno A LLARD , Dominique P LANSON Laboratoire Ampère, Lyon, France 8/7/13 1 / 26
Outline Introduction Selection of Power Devices Custom Gate Drive Prototype and Test Setup Results Conclusion 2 / 26
Outline Introduction Selection of Power Devices Custom Gate Drive Prototype and Test Setup Results Conclusion 3 / 26
The More Electric Aircraft ◮ Increase in on-board electric power: ◮ More than 1 MW for the B787 ◮ Need for higher voltage network: 540 V DC ◮ Electric actuators in harsh environment: ◮ Jet engine controls (e.g. thrust reverser controls) ◮ Electric brakes Requirements: ◮ Strong thermal cycling (-55/+200° C) ◮ Long operating life (target 30 years) ◮ Excellent reliability 4 / 26
High Temperature Inverter building blocks Power module: ◮ 6 JFETs in an hermetic package ◮ T A = 200 ◦ C , I out = 6 A per phase, 20 kHz < F SW < 300 kHz Gate drivers ◮ Integrated technology (SOI) ◮ Development of many functions ◮ Output buffer, signal conditionning ◮ Safety functions ◮ Temperature compensation EMI filter ◮ Characterization of passives for wide temperature operation (25/250° C) ◮ Evaluation of long-term ageing (>1000 h at 200° C) 5 / 26
Outline Introduction Selection of Power Devices Custom Gate Drive Prototype and Test Setup Results Conclusion 6 / 26
Overview of SiC Power Devices MOSFET ◮ Easy to drive, much like a silicon MOSFET ◮ “Normally-off” device ◮ Gate oxide reliability issues at high temperature 7 / 26
Overview of SiC Power Devices MOSFET ◮ Easy to drive, much like a silicon MOSFET ◮ “Normally-off” device ◮ Gate oxide reliability issues at high temperature JFET ◮ “Mature” device ◮ No gate oxide, making it very reliable at high temperature ◮ The chosen device is a “Normally-on” device 7 / 26
Overview of SiC Power Devices MOSFET ◮ Easy to drive, much like a silicon MOSFET ◮ “Normally-off” device ◮ Gate oxide reliability issues at high temperature JFET ◮ “Mature” device ◮ No gate oxide, making it very reliable at high temperature ◮ The chosen device is a “Normally-on” device BJT ◮ Reliability affected by substrate material quality ◮ “Normally-off” ◮ Driving not as simple as with FET devices 7 / 26
Forward characteristic of the SiCED JFET ◮ 4.08 × 4.08 mm 2 SiC die -50 ◦ C -10 ◦ C 27 ◦ C 70 ◦ C 107 ◦ C 70 ◮ Purchased in 2009 60 ◮ Manufactured by SiCED 160 ◦ C Drain current [A] 50 ◮ Normally-on 196 ◦ C 40 (off for V gs < − 21 V ) 234 ◦ C 270 ◦ C ◮ Tested up to 300° C 30 20 10 0 0 2 4 6 8 10 12 Drain-to-Source voltage [V] I D ( V DS ) characteristic for V GS = 0 V 8 / 26
Gate Characteristic 0 . 0 V GS is limited by punch-through − 0 . 2 ◮ Depends on current Gate current [mA] capability of the driver − 0 . 4 -50 ◦ C 130 ◦ C -30 ◦ C 150 ◦ C -10 ◦ C 170 ◦ C − 0 . 6 10 ◦ C 190 ◦ C 30 ◦ C 210 ◦ C 50 ◦ C 230 ◦ C − 0 . 8 70 ◦ C 250 ◦ C 90 ◦ C 270 ◦ C 110 ◦ C 290 ◦ C − 1 . 0 − 30 − 25 − 20 − 15 − 10 V GS voltage [V] 9 / 26
Gate Characteristic − 20 V GS is limited by punch-through − 22 ◮ Depends on current − 24 capability of the driver − 26 V GS [V] To block the JFET we need − 28 ◮ V GS < V th − 30 − 32 − 34 V GS Threshold voltage ( V th ) − 50 0 50 100 150 200 250 300 Junction temperature [ ◦ C] 9 / 26
Gate Characteristic − 20 V GS is limited by punch-through − 22 ◮ Depends on current − 24 capability of the driver − 26 V GS [V] To block the JFET we need − 28 ◮ V GS < V th − 30 − 32 V GS Threshold voltage ( V th ) − 34 V GS punch-through voltage ( V pt ) at 10 µ A − 50 0 50 100 150 200 250 300 Junction temperature [ ◦ C] 9 / 26
Gate Characteristic − 20 V GS is limited by punch-through − 22 ◮ Depends on current − 24 capability of the driver − 26 V GS [V] To block the JFET we need − 28 ◮ V GS < V th − 30 No damage observed on the − 32 V GS Threshold voltage ( V th ) JFET, even for I G > 10 mA V GS punch-through voltage ( V pt ) at 10 µ A − 34 V GS punch-through voltage( V pt ) at 100 µ A − 50 0 50 100 150 200 250 300 Junction temperature [ ◦ C] 9 / 26
Gate Characteristic − 20 V GS is limited by punch-through − 22 ◮ Depends on current − 24 capability of the driver − 26 V GS [V] To block the JFET we need − 28 ◮ V GS < V th − 30 V GS Threshold voltage ( V th ) No damage observed on the − 32 V GS punch-through voltage ( V pt ) at 10 µ A JFET, even for I G > 10 mA V GS punch-through voltage( V pt ) at 100 µ A − 34 V GS punch-through voltage ( V pt ) at 1 mA − 50 0 50 100 150 200 250 300 Junction temperature [ ◦ C] A driver that can source 1 mA continuously ensures safe turning off up to very high temperature, with a wide V GS margin 9 / 26
Outline Introduction Selection of Power Devices Custom Gate Drive Prototype and Test Setup Results Conclusion 10 / 26
IC Technology Silicon on Insulator (SOI) is an established technology, which can be used for high temperature electronics: Honeywell (“Extreme Design: Developing integrated circuits for -55 degC to +250° C”, nov 2008) 11 / 26
Design of the Gate Driver ◮ Driving requirements for SiCED JFETs: ◮ On: 0 V ◮ Off: ≈ -24 V with 1 mA quiescent and ≈ 1 A peak ◮ Commercial IGBT drivers can’t be used ◮ Chosen technology: Smartis-1 (ATMEL): ◮ 0.8 µ m Bipolar-CMOS ◮ Partially-depleted SOI ◮ 3 AlSiCu metal layers ◮ Ti/AlSiCu/TiN interconnects 12 / 26
Driver IC V neg Dead-time Buffer V aux1 G In Level-shifter V aux2 Dead-time Buffer S GND local ◮ Functions: input signal conditionning, dead time, push-pull output ◮ Other blocks (UVLO, short circuit protection. . . ) are not used here ◮ No external insulation provided for power supply and driving signal 13 / 26
Example of Function Design for Wide Temp. Range Dead-time generation ◮ Delay generation uses RC networks ◮ Delay can be adjusted by using 1..4 capacitors ◮ Use of a Negative Temperature Coefficient resistor to oppose the increase in resistance with temperature 14 / 26
Example of Function Design for Wide Temp. Range Dead-time generation 500 Controls 1-3 ON 450 Controls 1-2 ON Control 1 ON 400 Controls OFF Dead-Time (ns) 350 300 250 200 150 100 −50 0 50 100 150 200 250 Temperature (°C) ◮ Delay generation uses RC networks ◮ Delay can be adjusted by using 1..4 capacitors ◮ Use of a Negative Temperature Coefficient resistor to oppose the increase in resistance with temperature 14 / 26
Outline Introduction Selection of Power Devices Custom Gate Drive Prototype and Test Setup Results Conclusion 15 / 26
What’s Inside and What’s Not? High-side gate driver V bus Dead-time Buffer Level-shifter Dead-time Buffer OUT Low-side gate driver Dead-time Buffer Level-shifter Dead-time Buffer GND 16 / 26
What’s Inside and What’s Not? High-side gate driver DC V bus DC Dead-time Buffer DC DC Level-shifter Dead-time Buffer DC OUT DC PWM generator Low-side gate driver DC DC Dead-time Buffer DC DC Level-shifter Dead-time Buffer DC DC GND ◮ Isolation functions (signal and power) ◮ PWM signal generation ◮ Large value decoupling capacitor (1 µ F ) 16 / 26
Pictures of the power module ◮ CuMo leadframe / NiFe frame case ◮ ceramic substrate (AlN) ≈ 20 × 30 mm 2 ◮ high temperature passives (Vishay, Presidio) ◮ Al wedge Wirebonds, except Au ball for driver ◮ Bonding: silver sintering 17 / 26
The Test Setup No encapsulation used ➜ V DC limited to 200 V Power module attached to a hotplate ➜ test from ambient to 315° C External components at room temp. ➜ signal and power isolation ➜ large DC capacitor Continuous operation on resistor 18 / 26
Outline Introduction Selection of Power Devices Custom Gate Drive Prototype and Test Setup Results Conclusion 19 / 26
Measurements 250 200°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 200°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 26
Measurements 250 210°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 210°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 26
Measurements 250 220°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 220°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 26
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