0.85 PEF with AC-coupled Inverter-Stacking for Noise Efficiency - PowerPoint PPT Presentation

An ECG Chopper Amplifier Achieving 0.92 NEF and 0.85 PEF with AC-coupled Inverter-Stacking for Noise Efficiency Enhancement Somok Mondal and Drew A. Hall University of California, San Diego

Outline • Motivation and Introduction • Noise Efficiency Enhancement by OTA Stacking • ECG Amplifier Architecture • Circuit Implementation • Simulation Results • Conclusion 2

Motivation World of IoTs and m-Health Miniaturized Wearable & Implantable Devices • Automated, remote monitoring • Early detection/diagnosis Major Challenges: • Continuous reliable monitoring via a small integrated unit • Ultra-low power sensing circuits with long battery life 3

ECG Acquisition Amplifier Power consumption Amplifies weak, low-bandwidth is noise-limited physiological signals Noise Efficiency Factor (NEF)  noise-current trade-off 2𝐽 tot 𝑂𝐹𝐺 = 𝑤 ni,RMS 𝑊 T 4𝑙 B 𝑈𝜌𝐶𝑋 Power Efficiency Factor (PEF)  noise-power trade-off 𝑄𝐹𝐺 = 𝑂𝐹𝐺 2 𝑊 DD 𝐽 tot : amplifier current, 𝑤 ni,RMS : input referred noise, 𝐶𝑋 : bandwidth, T : thermal voltage, 𝑈 : temperature, 𝑙 B : Boltzmann’s constant 𝑊 4

Noise Efficiency Limitation For a differential amplifier if Fundamental NEF Limit • only input diff-pair noise 𝟑 • devices in sub-threshold 𝑶𝑭𝑮 𝒑 = 𝝀 𝟑 ≅ 𝟑. 𝟏𝟑 𝜆 : gate-coupling coefficient typically ~ 0.7 NEF Improvements: Prior Art • Current Reuse [1]: Inverter-based OTA 𝐻 m = 𝑕 mn + 𝑕 mp 𝑶𝑭𝑮 = 𝑶𝑭𝑮 𝒑 / 𝟑 • Dual Supply [2]: [1] - Chae TNSRE ‘09 𝑸𝑭𝑮 ≅ 𝑸𝑭𝑮 𝒑 /𝟓 [2] - Yaul ISSCC ‘16 5

Proposed Stacked OTA AC-coupled inverter-based transconductor Equivalent small-signal model Stacked OTA 6

Proposed Stacked OTA 𝐻 m = 𝑶𝐻 mo [3] G m boosting: 𝑆 out = 𝑆 o /𝑶 𝐵 v = 𝐻 m 𝑆 out = 𝐻 mo 𝑆 o 𝐻 m , 𝑆 out : compound transconductance, output impedance 𝐻 m0 , 𝑆 o : single inverter transconductance, output impedance 𝐵 v : OTA Gain [3] - Iguchi ISSCC’16 (crystal oscillator start -up) 7

Proposed Stacked OTA 𝐻 m = 𝑂𝐻 mo G m boosting: Input-referred noise: = 4𝑙 B 𝑈𝛿 2 𝑤 ni,thermal 𝑶𝐻 mo 𝐿 p 1 𝐿 n 2 𝑤 ni,flicker = + 4𝑶𝑔 𝐷 ox 𝑋𝑀 n 𝐷 ox 𝑋𝑀 p 𝛿 , 𝐷 ox , 𝐿 n , 𝐿 p : device parameters 𝑋𝑀 n,p : device sizes 2 : input referred noise PSD 𝑤 ni Noise efficiency enhancement: • 𝟑𝑶 times improvement in 𝑂𝐹𝐺 • 𝟑𝑶 times improvement in 𝑄𝐹𝐺 (same 𝑊 DD ) For a differential 2-stack NEF limit : 1.01 implementation: 3-stack NEF limit : 0.82 8

Trade-offs Inverter-Stacking Trade-offs: 𝑊 DD,min = 𝑂𝑊 INV + 𝑊 tail 𝑂𝐹𝐺 ∝ 1/ 𝑂 𝑄𝐹𝐺 min ∝ 𝑊 𝐽𝑂𝑊 + 𝑊 tail /𝑂 𝑊 INV , 𝑊 tail : voltage headroom for single inverter, tail source Normalized minimum PEF: • 2-stack: 0.82 • 3-stack: 0.75 • 4-stack: 0.72 3-stack with 1 V supply is optimal 9

ECG Amplifier Architecture Key Challenges: • AC-coupling of low bandwidth ECG (~250 Hz) would require very large capacitors • Signal swing with OTA stacking is limited 10

ECG Amplifier Architecture Key Challenges: • AC-coupling of low bandwidth ECG (~250 Hz) would require very large capacitors • Upmodulate to a higher (chopping) frequency  simpler ac-coupling • Signal swing with OTA stacking is limited • First stage with low signal swing 11

ECG Amplifier Architecture Other Requirements: • Low in-band flicker noise • High CMRR (for 60Hz noise) • Electrode polarization offset • High input impedance 2 nd stage DC bias • 12

ECG Amplifier Architecture Other Requirements: • Low in-band flicker noise • High CMRR (for 60Hz noise) • Electrode polarization offset • High input impedance 2 nd stage DC bias • 13

ECG Amplifier Architecture Other Requirements: • Low in-band flicker noise • High CMRR (for 60Hz noise) • Electrode polarization offset • High input impedance 2 nd stage DC bias • 14

ECG Amplifier Architecture Other Requirements: • Low In-band flicker noise • High CMRR (for 60Hz noise) • Electrode polarization offset • High input impedance 2 nd stage DC bias • 15

Circuit Implementation Fully Differential Stacked OTA: • 𝐷 ci , 𝐷 co , 𝐷 Dn,p  low impedance (ac-shorts) at the chopping frequency (5 kHz) • 𝐷 Dn,p are 25 pF MOS capacitors to account for 1/𝑕 m source impedance ~ 6M Ω . (40 × 40 μm 2 ) • Differential operation aids the decoupling with source nodes acting as virtual shorts. 16

Circuit Implementation Mid-band gain: Fully Differential Stacked OTA: 𝐷 Ci 𝑂𝐷 co 𝐵 M1 = − 𝐻 mo 𝑆 o 𝐷 ci + 𝐷 in,tot 𝑂𝐷 co + 𝐷 L1 Large 𝐷 L1 required for Miller compensation  Use load compensation used instead 𝐷 Ci,o are 4 pF MOM capacitors 17

Circuit Implementation 2 nd stage OTA: 𝑾 𝐃𝐍 generation: Design Summary: • 1 V Supply 1.2 nA (7%) 0.22 nA (1%) 2.3 nA (13%) Constant-G m bias: 14 nA (79%) 18

Simulation Results Stacked OTA simulations Open-loop gain Input-referred noise 19

Simulation Results Closed-loop amplifier simulations Amplifier differential-mode gain Amplifier loop-gain (using PAC analysis) (using PSTB analysis) Phase Margin ~ 90° 20

Simulation Results 100 monte-carlo runs (over process Amplifier transient and mismatch variations) response and spectra CMRR > 75 dB SFDR = 54 dB PSRR > 60 dB THD = 0.3% 21

Simulation Results Amplifier noise performance with inverter-stacking 148 nV /√Hz with only 14 nA! 22

Summary and Comparison Best reported NEF of 0.92 and PEF of 0.85! 23

Conclusion • AC-coupled Inverter-stacking for G m -boosting leading to noise efficiency enhancement • Best-reported NEF/PEF from simulations • Useful technique particularly for IoT mHealth applications 24

Backup Slides 25