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Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in - PowerPoint PPT Presentation

Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay October 30, 2014 1 / 9 Encoder State Diagram 1 + D 2 1 + D + D 2 G ( D ) = 1 + D 0/000 v ( 0 )


  1. Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay October 30, 2014 1 / 9

  2. Encoder State Diagram 1 + D 2 1 + D + D 2 � � G ( D ) = 1 + D 0/000 v ( 0 ) + S 0 0/011 1/111 1/100 u v ( 1 ) + S 2 S 1 0/101 0/110 1/010 v ( 2 ) + S 3 1/001 2 / 9

  3. Encoder Trellis Diagram 001 001 001 001 S 3 S 3 S 3 S 3 S 3 · · · 010 010 010 010 010 110 110 110 110 S 1 S 1 S 1 S 1 S 1 S 1 · · · 101 101 101 101 101 100 100 100 100 S 2 S 2 S 2 S 2 S 2 · · · 111 111 111 111 111 111 011 011 011 011 S 0 S 0 S 0 S 0 S 0 S 0 S 0 · · · 000 000 000 000 000 000 • The initial state of the encoder is the all-zeros state • Every path in the trellis starting from the initial state corresponds to a codeword 3 / 9

  4. Terminated Trellis Diagram 001 001 001 S 3 S 3 S 3 S 3 010 010 010 010 110 110 110 110 S 1 S 1 S 1 S 1 S 1 101 101 101 101 101 100 100 100 S 2 S 2 S 2 S 2 S 2 111 111 111 111 111 011 011 011 011 011 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 000 000 000 000 000 000 000 • The inputs are chosen to terminate the trellis in the all-zeros state • Every path from the initial state to the final state is a codeword 4 / 9

  5. Terminating the Trellis of Feedforward Encoders v ( 0 ) + v ( 1 ) u + v ( 2 ) + • Two consecutive zero input bits will drive the above encoder to the all-zeros state • In a feedforward encoder with memory order m , m consecutive zero input bits in each of the k inputs will terminate the trellis 5 / 9

  6. Terminating the Trellis of Feedback Encoders v i + + · · · + + f 0 f 1 f 2 f m − 1 f m u i w i w i − 1 w i − 2 w i − m + · · · q 1 q 2 q m − 1 q m + + + · · · • To reach the all-zeros state, the input to the shift register has to be zero for m time units m � w i = 0 = ⇒ u i = q j w i − j j = 1 6 / 9

  7. Maximum Likelihood Decoder for BSC 001 001 001 S 3 S 3 S 3 S 3 010 010 010 010 110 110 110 110 S 1 S 1 S 1 S 1 S 1 101 101 101 101 101 100 100 100 S 2 S 2 S 2 S 2 S 2 111 111 111 111 111 011 011 011 011 011 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 000 000 000 000 000 000 000 • Let r = � � 110 110 110 111 010 101 101 be the BSC output • The ML decoder will output a codeword v such that d H ( r , v ) is minimum • The Viterbi algorithm is an efficient way to find the v closest to r 7 / 9

  8. Maximum Likelihood Decoder for BSC 3 2 2 S 3 S 3 S 3 S 3 1 1 2 0 3 2 2 2 S 1 S 1 S 1 S 1 S 1 2 2 1 3 0 3 2 2 S 2 S 2 S 2 S 2 S 2 1 1 1 0 2 2 1 1 2 2 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 2 2 2 3 1 2 2 • Branch metric is the Hamming distance between the codeword bits of a state transition and the corresponding received bits • Path metric is the sum of all the branch metrics along a path 8 / 9

  9. Questions? Takeaways? 9 / 9

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