Advanced VLSI Design Memory CMPE 640 Memory Can be categorized into: • Read Write Memory (RWM) • Random Access Memory (RAM): static SRAM (faster) verses dynamic DRAM (smaller) structures possible. Access time independent of physical location of data. • Non-RAM: Serial Access Memory (FIFO, LIFO, Shift register) and Con- tent Access Memory (CAM). Non-uniform access time. • Non-volatile Read Write Memory (NVRWM): write time much larger than read time. • EPROM, E 2 PROM, FLASH • Read Only Memory (ROM) A second classification for RAMs and ROMs: • Static-load: no clock required. • Synchronous: require a clock edge to enable memory operation. • Asynchronous: recognize address changes and output new data. More difficult to build. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 1 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Memory Architecture In order to build an N-word memory where each word is M bits wide (typi- cally 1, 4 or 8 bits), a straightforward approach is to stack memory: A word is selected by setting exactly S 0 one of the select bits, S x , high. Word 0 S 1 Word 1 S 2 Storage cell Word 2 N words This approach works well for small memories but has problems for large memories. S N-2 Word N-2 For example, to build a 1Mword S N-1 Word N-1 (where word = 8 bits) memory, requires 1M select lines, provided by some off-chip device. Input-Output (M bits) This approach is not practical. What can we do? L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 2 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Memory Architecture Add a decoder to solve the package problem: S 0 Binary encoded address Word 0 S 1 Word 1 A 0 S 2 Storage cell Word 2 A 1 Decoder A 2 This reduces the A K-1 number of external address pins from S N-2 Word N-2 1M to 20. S N-1 Word N-1 K = log 2 N Input-Output one-hot (M bits) This does not address the memory aspect ratio problem: The memory is 128,000 time higher than wide (2 20 /2 3 ) ! Besides the bizarre shape factor, the design is extremely slow since the ver- tical wires are VERY long (delay is at least linear to length). L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 3 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Memory Architecture The vertical and horizontal dimensions are usually very similar, for an aspect ratio of unity . Multiple words are stored in each row and selected simultaneously: Bit line S 0 Row address = Storage cell A K to A L-1 S 1 A K S 2 Row Decoder A K+1 A K+2 Word line A L-1 S N-2 S N-1 Column address = A 0 to A K-1 A 0 Sense amps Column decoder A K-1 and drivers not shown A column decoder is added to Input-Output select the desired word from a row. (M bits) L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 4 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Memory Architecture This strategy works well for memories up to 64 Kbits to 256 Kbits. Larger memories start to suffer excess delay along bit and word lines. A third dimension is added to the address space to solve this problem: Block 0 Block i Block P-1 Row Address Column Address Block Block selector Address Global Data bus 4 Mbit: P = 32 blocks with 128Kbits/block. Global Address: [ Row ][ Block ][ Col ] amplifier/driver 128Kbit block: 1024 rows and 128 columns. I/O L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 5 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Memory: Architecture An example: 2 m+k bits A k Row decoder A k +1 Row decoder 2 n-k bits Row decoder A n-1 Row decoder A 0 Column decoder column mux, sense amp, write buffers A k-1 [A n-1 ..A k ][A k-1 ..A 0 ] For example: Let N = 1,048,576 and M = 8 bits for a 1 million byte memory. n = log 2 N = 20, k = 8 and m = log 2 M = 3. Then there are 2 n-k rows = 2 12 = 4096 and 2 k+m columns/2 3 bits per word = 2 8 = 256 words. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 6 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 ROM ROM cells are permanently fixed: Several possibilities: BL BL BL WL WL WL 1 psuedo n-MOS BL NOR gate. WL WL BL WL 0 Resistance of n/p should be at least 4. Diode supplies current BJT supplies current p-MOS used to hold to raise BL (bitline) for to raise BL for each BL high. n-MOS all cells on the row. cell on the row. Requires provides pull-down V DD to be routed. path. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 7 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Non-volatile Read-Write Memories Virtually identical in structure to ROMs. Selective enabling/disabling of transistors is accomplished through modifi- cations to threshold voltage . This is accomplished through a floating gate. 20V Source Drain Gate -5V after t ox Floating Gate programming - - - - - - - - this device off t ox 20V - n+ n+ Substrate Applying a high voltage (15 to 20 V) between source and gate-drain create high electric field and causes avalanche injection to occur. Hot electrons traverse first oxide and get trapped on floating gate, leaving it negatively charged. This increases the threshold voltage to ~7V. Applying 5V to the gate does not permit the device to turn on. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 8 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Non-volatile Read-Write Memories The method of erasing is the main differentiating factor between the various classes of reprogrammable nonvolatile memories. • EPROM : UV light renders oxide slightly conductive. Erase is slow (seconds to several minutes). Programming is slow (5-10 microsecs per word). Limited number of programming cycles - about 1000. Very dense - single transistor functions as both the programming and access device. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 9 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Non-volatile Read-Write Memories • EEPROM or E 2 PROM : Very thin oxide allows electrons to fl ow to and fr om the gate via Fowler- Nordheim tunneling with V GD applied. Erasure is achieved by reversing the voltage applied during writing. Source Drain Gate 10V t ox Floating Gate - - - - - - - - t ox thin tunneling ox n+ n+ Substrate BL WL Threshold control becomes a problem: Removing too much charge results in a V DD depletion device that cannot be turned off. Remedy: Add an access transistor. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 10 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Non-volatile Read-Write Memories • Flash EEPROM : Combines density adv. of EPROM with versatility of EEPROM. Uses avalanche hot-electron-injection approach to program. Erasure performed using Fowler-Nordheim tunneling. Monitoring control hardware checks the value of the threshold during erasure - making sure the unprogrammed transistor remains an enhancement device. 12V Source Drain Gate 12V t ox 12V Floating Gate - - - - - - - - erasure thin tunneling ox - n+ n+ - programming Substrate Programming performed by applying 12V to gate and drain. Erasure performed with gate grounded and source at 12V. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 11 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Read-Write Memories (RAM) SRAM: V DD word line bit bit L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 12 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Read-Write Memories (RAM) Generic RAM circuit: clocks Bit Line Conditioning bit bit RAM cell row decoder n-1;k word line column decoder Sense Amp k-1;0 Column Mux Write Buffers Address write-data read-data L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 13 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Read-Write Memories (RAM) SRAM: Read Operation Precharging bit and bit_bar to 5V before enabling the word line improves performance. To optimize speed, use n-channels as precharge devices. precharge bit bit precharge V DD bit, bit word word data data L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 14 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
Advanced VLSI Design Memory CMPE 640 Read-Write Memories (RAM) SRAM: Write Operation: N 5 N 6 write-data 0 write cell cell word N 3 N 4 P bit 1->0 0->1 word bit, bit bit bit cell, cell N 1 write N 2 Zero stored in cell originally. write-data 1 N d , N 1 , and N 3 have to pull P bit below N d the inverter threshold. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 15 (12/8/04) I E S R C E O V U I N N U T Y 1 6 9 6
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