Two-Dimensional van der Waals Materials Based Nonvolatile Memory Field-Effect Transistors Do Kyung Hwang Center for Opto-Electronic Materials and Devices, Korea Institute of Science and Technology (KIST) dkhwang@kist.re.kr
2-D van der Waals Materials beyond Graphene Transition Metal Dichalcogenide (TMD) Black phosphorous (BP) M X Ti, Hf, Zr V, Nb, Ta S, Se, Te Mo, W Tc, Re Pd, Pt L. Li et al . Nat. Nanotechnol. 9 , 372 (2014) B. Radisavljevic et al . ACS Nano O. Lopez-Sanchez et al . Nat. Nanotechnol. 8 , 497 (2013) 5 , 9934 (2011) Y. Deng et al . ACS Nano 8 , 8292 (2014) Why 2D vdWs Nanosheets ? They are hot materials for future semiconductor. They have very high carrier mobility. They show a quantum confinement effect . 2
MoS 2 and BP ferroelectric FETs MoS 2 FeFETs BP FeFETs MoS 2 FeFET with graphene S/D BP FeFET unit device and Resistive-load inverter circuit V IN Load R Ext -(VDF)- -(TrFE)- (10 M Ω ) F F F F Gr Gr V D [ ] [ ] C C C C 70 30 Au/Ti Au/Ti H H F H BFM 02 V OUT MoS 2 P(VDF-TrFE) copolymer (W/L: ~ 0.5) 15 um p -BP and n -MoS 2 CMOS inverter circuit Au top gate P(VDF-TrFE) (220 nm) Graphene Graphene Source Drain MoS 2 nanoflake SiO 2 (285 nm) / p + -Si
MoS 2 FETs with Graphene S/D Direct imprinting method Transfer and output characteristics -3 -3 10 10 Au/Ti SD electrode V D = 1V Au/Ti SD electrode V D = 1V (a) (b) -4 -4 10 10 SiO 2 /p + Si Graphene SD electrode Graphene SD electrode -5 -5 10 10 Gr2 Gr1 Drain Current (A) -6 -6 10 Drain Current (A) 10 MoS 2 -7 -7 10 10 y-axis -8 -8 10 10 Au Au 5um /Ti /Ti -9 -9 10 10 x-axis -10 -10 10 10 I G -11 -11 10 10 I G -12 -12 10 10 -13 -13 10 10 -50 -40 -30 -20 -10 0 10 20 30 40 50 -50 -40 -30 -20 -10 0 10 20 30 40 50 Gate Voltage (V) Gate Voltage (V) 15 15 20 20 Au/Ti SD electrode Au/Ti SD electrode (c) (d) Graphene SD electrode 15 Graphene SD electrode 15 10 10 V G = -50~50, 10V step V G = -50~50, 10V step Drain Current ( µ A) Graphene S/D electrode for MoS 2 10 10 Drain Current ( µ A) 5 5 5 5 0 0 0 0 (a) (b) 1.0 1.0 1.0 1.0 ∆ q Ф = q Ф Gr -q Ф MoS2 -5 -5 0.5 0.5 0.5 0.5 -5 -5 I D ( µ A) I D ( µ A) E 0 E 0 0.0 0.0 0.0 0.0 -10 -10 -0.5 -0.5 -10 -10 -0.5 -0.5 -15 -15 -1.0 -1.0 q Х MoS2 -1.0 -1.0 -0.5 0.0 0.5 q Ф G r -0.5 0.0 0.5 V D (V) V D (V) q Ф MoS2 q Ф MoS2 -15 -15 -20 -20 (= 4.0eV) q Ф Gr (= 4.5eV) (= 4.5eV) -1.0 -0.5 0.0 0.5 1.0 -1.0 -0.5 0.0 0.5 1.0 (= 4.3eV) (= 4.3eV) Drain Voltage (V) Drain Voltage (V) q Ф SB,Gr < E C -E F + ∆ q Ф E C E C 0.3eV E F E F Graphene S/D electrode: superior ohmic or ON/OFF E V E V current behavior to those of Au/Ti due to modulated i i n work function according to applied gate bias Y. T. Lee et al . Small 10 , 2356 (2014) 4
MoS 2 based ferroelectric field-effect transistors (FeFETs) MoS 2 FeFET with P(VDF-TrFE) Dynamic and Retention properties 20 + 18.7V, 1 s (Program) V G Pulse (V) 10 -(VDF)- -(TrFE)- 0 V, 4 s 0 F F F F Gr (read) Gr -10 [ ] [ ] C C -20 -18.7 V, 1 s (Erase) C C 70 30 Au/Ti Au/Ti V D =0.1 V Program -8 H H F H 10 I D (A) MoS 2 -10 10 P(VDF-TrFE) copolymer (W/L: ~ 0.5) 15 um -12 10 Erase -14 10 0 10 20 30 40 50 60 Au top gate Time (s) P(VDF-TrFE) (220 nm) -4 10 Graphene Graphene V D =0.1 V Source Drain -6 10 MoS 2 nanoflake Drain Current (A) 1s +20V Program -8 SiO 2 (285 nm) / p + -Si 10 Floating gate 0V Read -10 10 1s 0V Read -4 210 10 Floating gate -1 ) Erase 175 cm 2 /Vs -12 -5 V D =1.0 V 10 10 -1 s -20V 180 1s -6 +20V 10 2 V Drain Current (A) Program 150 -7 Linear Mobility (cm -14 10 10 0V 0 1 2 3 4 5 6 7 8 9 10 -8 10 120 Time (min) -9 10 1s 90 0V -10 10 -11 60 10 -20V MoS 2 FeFET : Highest mobility of 175 cm 2 /V s , memory -12 10 30 Erase -13 10 window > 15 V, proper dynamic and retention properties 0 -14 10 -20 -10 0 10 20 Gate Voltage (V) 5 Y. T. Lee et al . J. Korean Phys. Soc. Inpress (2015)
BP based FeFETs and Memory circuits (1) BP FeFET with P(VDF-TrFE) Linear Mobility 140 BFM 01 V D = -0.1 V 120 131 cm 2 V -1 s -1 -1 ) 100 -1 s 80 2 V lin (cm 60 40 µ 20 0 -20 -10 0 10 20 V G (V) Memory static and retention properties -4 10 1s V D = -0.1 V V D = -0.1 V 0V 1s -6 10 Read 0V Floating gate V G Memory window -6 -20V 10 -20V -8 10 : 15 V Program Program - I D (A) V D - I D (A) -8 10 Memory on-off 1s -10 +20V 10 : 10 6 Floating gate Erase 0V Read -10 10 -12 10 1s Mobility +20V Erase : 131 cm 2 /Vs -14 -12 0V 10 10 -20 -10 0 10 20 1 10 100 1000 V G (V) Time (s) 6 Y. T. Lee et al . ACS Nano DOI: 10.1021/acsnano.5b04592 (2015)
BP based FeFETs and Memory circuits (2) Resistive-load inverter circuit p -BP and n -MoS 2 CMOS inverter circuit V IN Common gate Load R Ext (10 M Ω ) 3 rd BP flake W/L: ~0.55 V DD MoS 2 flake W/L: ~1.06 BFM 02 V OUT V DD = -0.1 V BFM 02 1s 10 -4 10 +20V Height (nm) Erase 8 BP V D = ± 0.1 V 6 -6 BFM 03 0V 10 V DD 4 ~ 7.2 nm Abs(I D ) (A) 15 V 2 R Ext -8 10 10 M Ω 0 V BG =0 V V OUT 16 V BG =5 V 1s -10 Height (nm) MoS 2 10 V BG =10 V 0V 12 V IN V BG =15 V BFM 02 Program V BG =20 V 8 -12 10 -20V ~ 12.5 nm MFM 03 4 -14 0 10 -20 -10 0 10 20 0.0 0.4 0.8 1.2 1.6 2.0 V TG (V) Distance ( µ m) 0.12 0.12 0.12 BFM 02 V BG =20 V, V DD = 0.1 V V DD = -0.1 V V BG =20 V, V DD = 0.1 V 0.10 0.10 0.10 Erase 1s 1s +20V Erase +20V 1s 0.08 0.08 Erase 0.08 +20V V OUT (V) V OUT (V) - V OUT (V) V IN : Floating V IN 0V Read 0V 0.06 Floating gate 0.06 0.06 0V Read BFM 03 0.04 V DD 0.04 1s 1s 0V Read 0.04 0V 1s V OUT V BG V IN : Floating Read 0.02 0V MFM Program Program 0.02 Floating gate -20V GND -20V 0.02 0.00 Program -20V 0.00 -20 -10 0 10 20 0 100 200 300 400 0.00 V IN (V) Time (s) 1 10 100 1000 7 Y. T. Lee et al . ACS Nano DOI: 10.1021/acsnano.5b04592 (2015) Time (s)
Summary We demonstrate the high performance MoS 2 based nonvolatile memory transistors High performance, clear memory window, proper dynamic and retention properties Papers: Y. T. Lee et al. Small 10, 2356 (2014) and J. Korean Phys. Soc Inpress (2015) We also demonstrate few-layered BP-based nonvolatile memory transistors and more advanced memory circuits. Unit device, resistive-load inverter, and CMOS inverter combined with MoS 2 Paper: Y. T. Lee et al. ACS Nano DOI: 10.1021/acsnano.5b04592 (2015) 8
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