Triple Patterning Lithography (TPL) Layout Decomposition using - - PowerPoint PPT Presentation

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting

Bei Yu, Jhih-Rong Gao, and David Z. Pan

• Dept. of Electrical & Computer Engineering

University of Texas at Austin Supported in part by NSF, SRC, Oracle, and NSFC

Triple Patterning Lithography (TPL)

t LELE-LE: Extend from LELE type double patterning t Main challenge: layout decomposition t Native conflicts

2

a b c d

Target/ Final 1st Mask 2nd Mask 3rd Mask

TPL with End-Cutting (LELE-EC)

t New TPL manufacturing process [Lin, ISPD’12] t LELE + end cutting (trim mask)

3

Target/ Final 1st Mask 2nd Mask Trim Mask

Why LELE-EC ?

t Remove 4-clique native conflict in LELE-LE

› Common even in regular layout

t Square-shaped Line-ends

4

a b c d

[B. Lin, ISPD’12] [Y. Bordovsky, SPIE’05]

LELE-EC: no free lunch

t New design constraints:

› Min distance among end-cuts

5

Stitch

Solution to simultaneously assign colors and assign end-cuts

Previous Works

t LELE-LE layout decomposition

› Mathematical programming [Cork, SPIE’08; Yu, ICCAD’11] › Heuristic methods [Ghaida, SPIE’12; Fang, DAC’12] › Polynomial time checking [Tian, ICCAD’12/SPIE’13]

t LELE-LE aware routing [Ma, DAC’12; Lin, ICCAD’12] t First study for LELE-EC type triple patterning

› Can borrow previous idea ?

6

Layout Decomposition Flow

7

End-cut Candidate Generation Layout Graph and End-cut Graph Decomposition on Graph Output Masks ILP Formulation Simplification

Layout Decomposition Rules

End-cut Candidate Generation

t Edge-edge t Corner-corner

8

(a) (b) (c) (d)

(a) (b) (c) (d)

Layout Decomposition Flow

9

End-cut Candidate Generation Layout Graph and End-cut Graph Decomposition on Graph Output Masks ILP Formulation Simplification

Layout Decomposition Rules

Layout Graph

t Layout topologies è graph model t Layout graph: feature info and end-cut candidate info

10

1 2 3 4 5 6 7

1 2 3 4 5 6 7

5-7 6-7 2-4 1-4 3-4 4-6 1-3 3-5 5-6 1- 2

1 2 3 4 5 6 7

4 6 1 2 3 5 7

Conflict edge that can be removed by end-cut

End-cut graph

t Some end-cuts are conflict, while some can be merged t New graph to store the end-cut relationships

› conflict edge (solid): two candidates are conflict › merge edge (dash): two candidates can be merged

11

5-7 6-7 2-4 1-4 3-4 4-6 1-3 3-5 5-6 1- 2

1 2 3 4 5 6 7

1-3 1-2 2-4 3-4 1-4 4-6 3-5 5-6 6-7 5-7

ec14 and ec46 have conflict ec35 and ec46 can be merged into one endcut

4 6 1 2 3 5 7

Conflict edge that can be removed by end-cut

Layout Decomposition Flow

12

End-cut Candidate Generation Layout Graph and End-cut Graph Decomposition on Graph Output Masks ILP Formulation Simplification

Layout Decomposition Rules

ILP Formulation

t CE: edge set of layout graph t EE: conflict-edge set of end-cut graph

13

1-2 1-3 2-3

1 2 3 1 2 1 2 3

Exception: x1=x2, since ec13=ec23=1, ec12 can be 0

ILP Formulation (cont.)

14

1-2 1-3 2-3

1 2 3 1 2 1 2 3

Non-linear

ILP Formulation (cont.)

t Consider stitch insertion t SE: set of stitch edge candidates

15

Other constraints in previous ILP

Layout Decomposition Flow

16

End-cut Candidate Generation Layout Graph and End-cut Graph Decomposition on Graph Output Masks ILP Formulation Simplification

Layout Decomposition Rules

t Independent Component Computation t Bridge Computation t End-Cut Pre-Selection

Experimental Results

t Implement in C++ t 3.0GHz Linux machine with 32G RAM t ISCAS 85&89 benchmarks from [Yu, ICCAD’11] t Scaled to 14nm nodes t ILP solver: GUROBI

17

Without or With stitch?

t Cost comparison (cost = conflict# + 0.1 * stitch#) t Runtime comparison

18

45 50 C432 C499 C880 C1,355 C1,908 C2,670 C3,540 C5,315 C6,288 C7,552 S1,488 S38,417 S35,932 S38,584 S15,850 Cost = Conflict + 0.1 * Stitch

ILP w/o. stitch ILP w. stitch

5 10 15 20 25 30 35 40 C3,540 C5,315 C6,288 C7,552 S1,488 S38,417 S35,932 S38,584 S15,850 Runtime (s)

ILP w/o. stitch ILP w. stitch

100 200 300 400 500 600 C432 C499 C880 C1,355 C1,908 C2,670

cost runtime

Conflict Example

19

t Irregular via array is dangerous

LELE-LE v.s. LELE-EC

t LELE-LE decomposer from [Fang, DAC’12]

20

10 15 20 25 30 35 40 45 50 C432 C499 C880 C1,355 C1,908 C2,670 C3,540 C5,315 C6,288 C7,552 S1,488 S38,417 S35,932 S38,584 S15,850 Conflict Num

LELELE LELEEC

5 100 150 200 250 300 350 C432 C499 C880 C1,355 C1,908 C2,670 C3,540 C5,315 C6,288 C7,552 S1,488 S38,417 S35,932 S38,584 S15,850 Stitch Num

LELELE LELEEC

50

conflict stitch

Conclusion and Future Works

t First LELE-EC layout decomposition problem t ILP formulation and speedup techniques t Less conflict & stitch compared with LELE-LE

TPL is candidate for 14nm node.

t More research on TPL(LELEEC)-aware design

21

Thank You

22