Layout Compliance for Triple Patterning Lithography: An Iterative Approach Bei Yu † , Gilda Garreton ‡ , David Z. Pan † † ECE Dept. University of Texas at Austin, Austin, TX, USA ‡ Oracle Labs, Oracle Corporation, Redwood Shores, CA, USA 09/16/2014 1 / 27
Outline Introduction New Challenges in Triple Patterning Lithography (TPL) Layout Compliance Algorithms Results and Conclusions 2 / 27
Outline Introduction New Challenges in Triple Patterning Lithography (TPL) Layout Compliance Algorithms Results and Conclusions 3 / 27
Lithography Status & Challenges 10 [Courtesy Intel] 1 um 0.1 X 1980 1990 2000 2010 2020 Advanced lithography to extend 193nm lithography ◮ Now and near future: double/triple/quadruple patterning ◮ Long term future: other advanced lithography 4 / 27
From Double Patterning to Triple Patterning Mask 1 ITRS roadmap 28nm Single Patterning Mask 2 22nm Double Patterning 14nm Triple Patterning 11nm Quadruple Patterning stitch Mask 1 Mask 2 Mask 3 ◮ Layout decomposition ◮ Patterning friendly design 5 / 27
Previous Works in TPL Layout Decomposition ◮ ILP or SAT [Cork+,SPIE’08][Yu+,ICCAD’11][Cork+,SPIE’13] ◮ Greedy or Heuristic [Ghaida+,SPIE’11][Fang+,DAC’12] [Kuang+,DAC’13][Yu+,DAC’14][Fang+,SPIE’14] ◮ SDP or Graph based (trade-off) [Yu+, ICCAD’11][Chen+,ISQED’13][Yu+,ICCAD’13] Limitations: can NOT guarantee TPL friendly (a) (b) 6 / 27
Layout Compliance Problem Formulation Input: ◮ Input layout patterns (may not be TPL friendly) ◮ Minimum coloring distance min s c c c a1 a1 a a2 a2 b b b d1 d1 d d2 d2 (a) (b) (c) Output: ◮ Apply layout decomposition and layout modification ◮ Remove all conflicts 7 / 27
Layout Decomposition v.s. Layout Compliance c c c a a a b b b d d d (a) Input layout (b) Layout decomposition (c) Layout Modification Layout Compliance = Layout Decomposition + Layout Modification 8 / 27
Outline Introduction New Challenges in Triple Patterning Lithography (TPL) Layout Compliance Algorithms Results and Conclusions 9 / 27
Challenge 1: NO Shortcut in TPL Complexity Optimizing conflict & stitch simultaneously is NP-hard for DPL/TPL. Shortcut in DPL : ◮ Step by step ◮ Each step can be optimally solved Step 1: Step 2: Input Layout Conflict Minimization Stitch Minimization (a) (b) (c) TPL : ◮ NO such shortcut, as conflict minimization is NP-hard ◮ Door closed? 10 / 27
Challenge 2: Where do the conflicts come from? DPL : ◮ Detect odd-cycle ◮ Long pattern chains (a) (b) TPL : ◮ NP-hard to detect ◮ But mostly local 4-clique (a) (b) (c) 11 / 27
Challenge 3: Decomposer – Clutching at Straws Conflict # Greedy or heuristic: Fast but bad quality SDP or graph search: Tradeoff, still not good in performance ILP: Good performance but expensive Performance target CPU runtime ◮ Gap ◮ Our performance target 12 / 27
Outline Introduction New Challenges in Triple Patterning Lithography (TPL) Layout Compliance Algorithms Step 1: Initial Layout Decomposition Step 2: Layout Modification Step 3: Incremental Layout Decomposition Results and Conclusions 13 / 27
Overall Flow Input Decomposition Graph Layout Construction 1. Fast Initial Layout Decomposition 2. Layout Modification 3. Incremental Layout Decomposition Output Masks 14 / 27
Overall Flow Input Decomposition Graph c Layout Construction 1. Fast Initial Layout Decomposition a 2. Layout Modification b 3. Incremental Layout Decomposition d Output Masks 14 / 27
Overall Flow Input Decomposition Graph Layout c Construction a1 1. Fast Initial Layout Decomposition 2. Layout Modification a2 b 3. Incremental Layout d1 Decomposition Output Masks d2 14 / 27
Overall Flow native structure Input Decomposition Graph behind conflict Layout Construction c 1. Fast Initial Layout a1 Decomposition 2. Layout Modification a2 b 3. Incremental Layout d1 Decomposition Output Masks d2 14 / 27
Overall Flow Input Decomposition Graph Layout c Construction a1 1. Fast Initial Layout Decomposition 2. Layout Modification a2 b 3. Incremental Layout d1 Decomposition Output Masks d2 14 / 27
Overall Flow color re-assignment region Input Decomposition Graph Layout c Construction a1 1. Fast Initial Layout Decomposition 2. Layout Modification a2 b 3. Incremental Layout d1 Decomposition Output Masks d2 14 / 27
Overall Flow Input Decomposition Graph c Layout Construction 1. Fast Initial Layout Decomposition a 2. Layout Modification b 3. Incremental Layout Decomposition d Output Masks 14 / 27
Step 1: Initial Layout Decomposition native structure ◮ Our method: linear color assignment behind conflict c c a1 ◮ Linear runtime complexity [Yu+,DAC’14] a1 ◮ May leave some conflicts to Step 2 & 3 a2 a2 b b d1 d1 ◮ Much faster than ILP or SDP d2 d2 Runtime comparisions: 15 / 27
Step 1: Fast Layout Decomposition (cont.) ◮ But, Any coloring order results in Local Optimality ◮ Example: order a-b-c-d b c b c a a d d (a) (b) Half Pitch b b b c c c a a a d d d (c) (d) Color-Friendly Rules: ◮ a-c tend to be with the same color 16 / 27
Step 1: Fast Layout Decomposition (cont.) Peer Selection: ◮ Three orders would be processed simultaneously ◮ Best solution would be selected ◮ Still Linear runtime complexity Degree-Coloring 3Round-Coloring Sequence-Coloring 17 / 27
Step 1: Fast Layout Decomposition (cont.) Peer Selection: ◮ Whole problem → a set of components ◮ Different components have different dominant orders ◮ Overall better results than any single order 18 / 27
Fast Layout Decomposition Result Example ◮ Row by row ◮ Resolved in 0.1 second 19 / 27
Step 2: Layout Modification Initial layout decomposition output: native conflict is labeled: (a) (b) Layout modification to break down each four-clique: (a) (b) 20 / 27
Step 3: Incremental Layout Decomposition color re-assignment region ◮ Input : One layout region & stitch# bound c c a1 a1 ◮ Output : color re-assignment in the region ◮ Method : branch-and-bound a2 a2 b b d1 d1 ◮ Early return if satisfy stitch# bound d2 d2 Runtiem & stitch# bound trade-off: 21 / 27
Step 3: Incremental Layout Decomposition– Example (a) (b) (c) (d) a Decomposed result after initial layout decomposition. b All layout patterns to be re-assigned colors are labeled. c The constructed local decomposition graph. d The result of incremental layout decomposition. 22 / 27
Outline Introduction New Challenges in Triple Patterning Lithography (TPL) Layout Compliance Algorithms Results and Conclusions 23 / 27
Interfaced with open source tool Electric 24 / 27
Layout Compliance Results 25 / 27
Conclusions ◮ First attempt for TPL layout compliance ◮ Faciliating the advancement of patterning technique Conflict # Greedy or heuristic: Fast but bad quality SDP or graph search: Tradeoff, still not good in performance ILP: Good performance but expensive Performance target � CPU runtime Future works ◮ Timing issue ◮ Smarter automatically layout modification 26 / 27
Thank You ! 27 / 27
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