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SoCs and TLM Compilation Verification Extra-functional Conclusion Transaction-Level Models of Systems-on-a-Chip Can they be Fast, Correct and Faithful? Matthieu Moy Laboratoire dInformatique du Parallelisme Lyon, France February 2018

  1. SoCs and TLM Compilation Verification Extra-functional Conclusion Use of Extra-Functional Models Timing, Power consumption, Temperature Estimation CPU TLM process = ITC VGA Timer C++ code TLM Bus Data RAM Instruction RAM GPIO Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 12 / 70 >

  2. SoCs and TLM Compilation Verification Extra-functional Conclusion Use of Extra-Functional Models Timing, Power consumption, Temperature Estimation CPU TLM process = ITC VGA Timer C++ code TLM Bus Data RAM Instruction RAM GPIO 60 60 50 50 40 40 ? 30 30 20 20 10 10 0 ≈ 0 10 10 20 20 30 30 Estimated Actual Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 12 / 70 >

  3. SoCs and TLM Compilation Verification Extra-functional Conclusion Use of Extra-Functional Models Timing, Power consumption, Temperature Estimation Unmodified Power/Temperature-Aware Software CPU TLM process = ITC VGA Timer C++ code TLM Bus Data RAM Instruction RAM GPIO 60 60 50 50 40 40 ? 30 30 20 20 10 10 0 ≈ 0 10 10 20 20 30 30 Estimated Actual Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 12 / 70 >

  4. SoCs and TLM Compilation Verification Extra-functional Conclusion Summary: Expected Properties of TLM Programs SystemC/TLM Programs should Simulate fast, Satisfy correctness criterions, Reflect faithfully functional and extra-functional properties of the actual system. Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 13 / 70 >

  5. SoCs and TLM Compilation Verification Extra-functional Conclusion Outline Introduction: Systems-on-a-Chip, Transaction-Level Modeling 1 Compilation of SystemC/TLM 2 Verification of SystemC/TLM 3 Extra-Functional Properties in TLM 4 Conclusion 5 Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 13 / 70 >

  6. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC: Simple Example N1 N2 SC_MODULE(not_gate) { int sc_main(int argc, char **argv) { sc_in<bool> in; // Elaboration phase (Architecture) sc_out<bool> out; // Instantiate modules ... not_gate n1("N1"); void compute (void) { not_gate n2("N2"); // Behavior sc_signal<bool> s1, s2; bool val = in.read(); // ... and bind them together out.write(!val); n1.out.bind(s1); } n2.out.bind(s2); n1.in.bind(s2); SC_CTOR(not_gate) { n2.in.bind(s1); SC_METHOD(compute); sensitive << in; // Start simulation } sc_start(100, SC_NS); }; return 0; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 14 / 70 >

  7. SoCs and TLM Compilation Verification Extra-functional Conclusion Compiling SystemC $ g++ example.cpp -lsystemc $ ./a.out ... end of section? Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 15 / 70 >

  8. SoCs and TLM Compilation Verification Extra-functional Conclusion Compiling SystemC $ g++ example.cpp -lsystemc $ ./a.out But ... C++ compilers cannot do SystemC-aware optimizations C++ analyzers do not know SystemC semantics Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 15 / 70 >

  9. SoCs and TLM Compilation Verification Extra-functional Conclusion This section Compilation of SystemC/TLM 2 Front-end Optimization and Fast Simulation Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 15 / 70 >

  10. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC Front-End In this talk: Front-end = “Compiler front-end” (AKA “Parser”) Intermediate Front Back SystemC Representation end end Intermediate Representation = Architecture + Behavior Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 16 / 70 >

  11. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC Front-Ends When you don’t need a front-end: ◮ Main application of SystemC: Simulation ◮ Testing, run-time verification, monitoring. . . Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 17 / 70 >

  12. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC Front-Ends When you don’t need a front-end: ◮ Main application of SystemC: Simulation ◮ Testing, run-time verification, monitoring. . . ⇒ No reference front-end available on http://www.accellera.org/ Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 17 / 70 >

  13. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC Front-Ends When you don’t need a front-end: ◮ Main application of SystemC: Simulation ◮ Testing, run-time verification, monitoring. . . ⇒ No reference front-end available on http://www.accellera.org/ When you do need a front-end: ◮ Symbolic formal verification, High-level synthesis ◮ Visualization ◮ Introspection ◮ SystemC-specific Compiler Optimizations ◮ Advanced debugging features Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 17 / 70 >

  14. SoCs and TLM Compilation Verification Extra-functional Conclusion Challenges and Solutions with SystemC Front-Ends C++ is complex (e.g. clang ≈ 200,000 LOC) 1 Architecture built at runtime, with C++ code 2 SC_MODULE(not_gate) { int sc_main(int argc, char **argv) { sc_in<bool> in; // Elaboration phase (Architecture) sc_out<bool> out; not_gate n1("N1"); void compute (void) { not_gate n2("N2"); // Behavior sc_signal<bool> s1, s2; bool val = in.read(); // Binding out.write(!val); n1.out.bind(s1); } n2.out.bind(s2); n1.in.bind(s2); SC_CTOR(not_gate) { n2.in.bind(s1); SC_METHOD(compute); sensitive << in; // Start simulation } sc_start(100, SC_NS); return 0; }; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 18 / 70 >

  15. SoCs and TLM Compilation Verification Extra-functional Conclusion Challenges and Solutions with SystemC Front-Ends C++ is complex (e.g. clang ≈ 200,000 LOC) 1 � Write a C++ front-end or reuse one (g++, clang, EDG, . . . ) Architecture built at runtime, with C++ code 2 � Analyze elaboration phase or execute it SC_MODULE(not_gate) { int sc_main(int argc, char **argv) { sc_in<bool> in; // Elaboration phase (Architecture) sc_out<bool> out; not_gate n1("N1"); void compute (void) { not_gate n2("N2"); // Behavior sc_signal<bool> s1, s2; bool val = in.read(); // Binding out.write(!val); n1.out.bind(s1); } n2.out.bind(s2); n1.in.bind(s2); SC_CTOR(not_gate) { n2.in.bind(s1); SC_METHOD(compute); sensitive << in; // Start simulation } sc_start(100, SC_NS); return 0; }; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 18 / 70 >

  16. SoCs and TLM Compilation Verification Extra-functional Conclusion Challenges and Solutions with SystemC Front-Ends C++ is complex (e.g. clang ≈ 200,000 LOC) 1 � Write a C++ front-end or reuse one (g++, clang, EDG, . . . ) Architecture built at runtime, with C++ code 2 � Analyze elaboration phase or execute it SC_MODULE(not_gate) { int sc_main(int argc, char **argv) { sc_in<bool> in; // Elaboration phase (Architecture) sc_out<bool> out; not_gate n1("N1"); Dynamic Approaches void compute (void) { not_gate n2("N2"); // Behavior sc_signal<bool> s1, s2; bool val = in.read(); // Binding Static Approaches out.write(!val); n1.out.bind(s1); } n2.out.bind(s2); n1.in.bind(s2); SC_CTOR(not_gate) { n2.in.bind(s1); SC_METHOD(compute); sensitive << in; // Start simulation } sc_start(100, SC_NS); return 0; }; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 18 / 70 >

  17. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with the architecture When it becomes tricky. . . int sc_main(int argc, char **argv) { int n = atoi(argv[1]); int m = atoi(argv[2]); Node array[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { array[i][j] = new Node(...); ... } } sc_start(100, SC_NS); return 0; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 19 / 70 >

  18. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with the architecture When it becomes tricky. . . int sc_main(int argc, char **argv) { int n = atoi(argv[1]); int m = atoi(argv[2]); Static approach: cannot Node array[n][m]; deal with such code for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { Dynamic approach: can array[i][j] extract the architecture for = new Node(...); ... individual instances of the } system } sc_start(100, SC_NS); return 0; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 19 / 70 >

  19. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with the architecture When it becomes very tricky. . . void compute(void) { for (int i = 0; i < n; i++) { ports[i].write(true); } ... } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 20 / 70 >

  20. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with the architecture When it becomes very tricky. . . One can unroll the loop to void compute(void) { let i become constant, for (int i = 0; i < n; i++) { ports[i].write(true); Undecidable in the general } case. ... } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 20 / 70 >

  21. SoCs and TLM Compilation Verification Extra-functional Conclusion The beginning: Pinapa AKA “my Ph.D’s front-end” Pinapa’s principle: ◮ Use GCC’s C++ front-end ◮ Compile, dynamically load and execute the elaboration ( sc_main ) Pinapa’s drawbacks: ◮ Uses GCC’s internals (hard to port to newer versions) ◮ Hard to install and use, no separate compilation ◮ Ad-hoc match of SystemC constructs in AST ◮ AST Vs SSA form in modern compilers Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 21 / 70 >

  22. SoCs and TLM Compilation Verification Extra-functional Conclusion LLVM: Low Level Virtual Machine JIT C++ compilation Front Back C Bitcode ends ends Code ... Generation Optimizer Clean API Clean SSA intermediate representation Many tools available Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 22 / 70 >

  23. SoCs and TLM Compilation Verification Extra-functional Conclusion LLVM: Low Level Virtual Machine JIT C++ compilation Front Back C Bitcode ends ends Code ... Generation Optimizer Can we be here? Clean API Clean SSA intermediate representation Many tools available Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 22 / 70 >

  24. SoCs and TLM Compilation Verification Extra-functional Conclusion PinaVM: Enriching the bitcode SystemC Compilation (llvm-g++, llvm-link) LLVM bitcode Execute Identify elaboration SC constructs Architecture bitcode++ Intermediate Representation Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 23 / 70 >

  25. SoCs and TLM Compilation Verification Extra-functional Conclusion PinaVM: Enriching the bitcode ... SystemC port.write(data); ... Compilation (llvm-g++, llvm-link) ... %port = expr1(%this) SystemC construct %data = expr2 LLVM bitcode is still a normal function call write %port, %data ... %this not known Cannot compute %port Execute Identify elaboration SC constructs ... %port = expr1(%this) %data = expr2 %this Architecture bitcode++ SCWrite is fixed - data = ?? - port = ?? ... ... Execute %port = expr1(%this) dependencies %data = expr2 SCWrite � Process 0 → data d 0 � - data = Process 1 → data d 1 Intermediate Representation � Process 0 → port p 0 � - port = Process 1 → port p 1 ... Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 23 / 70 >

  26. SoCs and TLM Compilation Verification Extra-functional Conclusion Summary PinaVM relies on executability (JIT Compiler) for execution of: ◮ elaboration phase ( ≈ like Pinapa) ◮ sliced pieces of code Open Source: http://forge.imag.fr/projects/pinavm/ Still a prototype, but very few fundamental limitations ≈ 3000 lines of C++ code on top of LLVM Experimental back-ends for ◮ Execution (Tweto) ◮ Model-checking (using SPIN) Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 24 / 70 >

  27. SoCs and TLM Compilation Verification Extra-functional Conclusion This section Compilation of SystemC/TLM 2 Front-end Optimization and Fast Simulation Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 24 / 70 >

  28. SoCs and TLM Compilation Verification Extra-functional Conclusion Typical Transaction Journey CPU 0x6000 RAM 0x5000 0x3000 T2 0x2000 0x1000 T1 0x0000 Bus T1 T2 RAM Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

  29. SoCs and TLM Compilation Verification Extra-functional Conclusion Typical Transaction Journey CPU 0x6000 RAM 0x5000 ... port.write(addr,data); 0x3000 ... T2 0x2000 0x1000 T1 0x0000 Bus T1 T2 RAM status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

  30. SoCs and TLM Compilation Verification Extra-functional Conclusion Typical Transaction Journey CPU 0x6000 RAM 0x5000 ... port.write(addr,data); 0x3000 ... T2 0x2000 Address 0x1000 Decoding Forward method T1 0x0000 call to target socket Call virtual method on socket Bus Another virtual Forwarded to T1 T2 method call target socket RAM status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

  31. SoCs and TLM Compilation Verification Extra-functional Conclusion Typical Transaction Journey CPU 0x6000 RAM 0x5000 ... port.write(addr,data); 0x3000 ... T2 0x2000 Address 0x1000 Decoding Forward method T1 0x0000 call to target socket Call virtual method on socket Bus Another virtual Forwarded to T1 T2 method call target socket Ends-up calling target module’s RAM method status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

  32. SoCs and TLM Compilation Verification Extra-functional Conclusion Typical Transaction Journey CPU 0x6000 RAM 0x5000 ... port.write(addr,data); 0x3000 ... T2 0x2000 Address 0x1000 Forward method Decoding T1 0x0000 call to target socket Call virtual method on socket Bus Another virtual Forwarded to T1 T2 method call target socket Ends-up calling target module’s RAM method status write(addr,data) { mem[addr] = data; } Many costly operations for a simple functionality Work-around: backdoor access (DMI = Direct Memory Interface) ◮ CPU get a pointer to RAM’s internal data ◮ Manual, dangerous optimization Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

  33. SoCs and TLM Compilation Verification Extra-functional Conclusion Typical Transaction Journey CPU 0x6000 RAM 0x5000 ... port.write(addr,data); 0x3000 ... T2 0x2000 Address 0x1000 Forward method Decoding T1 0x0000 call to target socket Call virtual method on socket Bus Another virtual Forwarded to T1 T2 method call target socket Ends-up calling target module’s RAM method status write(addr,data) { mem[addr] = data; } Many costly operations for a simple functionality Work-around: backdoor access (DMI = Direct Memory Interface) ◮ CPU get a pointer to RAM’s internal data ◮ Manual, dangerous optimization Can a compiler be as good as DMI, automatically and safely? Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

  34. SoCs and TLM Compilation Verification Extra-functional Conclusion Basic Ideas Do statically what can be done statically ... ... considering “statically” = “after elaboration” Examples: ◮ Virtual function resolution ◮ Inlining through SystemC ports ◮ Static address resolution Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 26 / 70 >

  35. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with addresses Statically CPU 0x6000 RAM 0x5000 ... port.write(0x5500,data); 0x3000 ... T2 0x2000 0x1000 T1 0x0000 Bus RAM status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  36. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with addresses Statically CPU 0x6000 RAM 0x5000 ... port.write(0x5500,data); 0x3000 ... T2 0x2000 0x1000 T1 0x0000 Get actual port addr from PinaVM Bus RAM status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  37. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with addresses Statically CPU 0x6000 RAM 0x5000 ... port.write(0x5500,data); 0x3000 ... T2 0x2000 Follow path 0x1000 to bus T1 0x0000 Get actual port addr from PinaVM Bus RAM status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  38. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with addresses Statically CPU 0x6000 RAM 0x5000 ... port.write(0x5500,data); 0x3000 ... T2 0x2000 Follow path 0x1000 to bus Address T1 0x0000 Decoding Get actual port addr from PinaVM Bus RAM status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  39. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with addresses Statically CPU 0x6000 RAM 0x5000 ... port.write(0x5500,data); 0x3000 ... T2 0x2000 Follow path 0x1000 to bus Address T1 0x0000 Decoding Get actual port addr from PinaVM Bus Find target socket at this address RAM status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  40. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with addresses Statically CPU 0x6000 RAM 0x5000 ... port.write(0x5500,data); 0x3000 ... T2 0x2000 Follow path 0x1000 to bus Address T1 0x0000 Decoding Get actual port addr from PinaVM Bus Find target socket at this address Find function in target RAM module status write(addr,data) { mem[addr] = data; } Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  41. SoCs and TLM Compilation Verification Extra-functional Conclusion Dealing with addresses Statically 0x6000 CPU RAM 0x5000 ... port.write(0x5500,data); 0x3000 ... T2 0x2000 Follow path 0x1000 to bus Address T1 0x0000 Decoding Get actual port addr from PinaVM Bus Find target socket at this address Find function in target RAM module status write(addr,data) { mem[addr] = data; } Possible optimizations: ◮ Replace call to port.write() with RAM.write() ◮ Possibly inline it Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  42. SoCs and TLM Compilation Verification Extra-functional Conclusion Outline Introduction: Systems-on-a-Chip, Transaction-Level Modeling 1 Compilation of SystemC/TLM 2 Verification of SystemC/TLM 3 Extra-Functional Properties in TLM 4 Conclusion 5 Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

  43. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches SystemC Encoding Formal language Existing verifier Yes/No/Maybe Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 28 / 70 >

  44. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches T 1 × T 2 × T 3 × Sch T 1 × T 2 × T 3 Synchronous automata Asynchronous automata + scheduler Dedicated product SystemC Concurrent program T 1 × T 2 × T 3 T 1 × T 2 × T 3 × Sch Asynchronous product Asynchronous automata shared variable Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 29 / 70 >

  45. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches T 1 × T 2 × T 3 × Sch T 1 × T 2 × T 3 Synchronous automata Asynchronous automata + scheduler Dedicated product SystemC Concurrent program T 1 × T 2 × T 3 T 1 × T 2 × T 3 × Sch Asynchronous product Asynchronous automata shared variable Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 29 / 70 >

  46. SoCs and TLM Compilation Verification Extra-functional Conclusion Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

  47. SoCs and TLM Compilation Verification Extra-functional Conclusion Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton Scheduler Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

  48. SoCs and TLM Compilation Verification Extra-functional Conclusion Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton User code: Automatic translation Scheduler Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

  49. SoCs and TLM Compilation Verification Extra-functional Conclusion Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton User code: SystemC kernel: Automatic translation Direct semantics Scheduler Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

  50. SoCs and TLM Compilation Verification Extra-functional Conclusion Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton User code: SystemC kernel: Automatic translation Direct semantics Scheduler Communication: Direct semantics Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

  51. SoCs and TLM Compilation Verification Extra-functional Conclusion The SystemC scheduler Non-preemptive scheduler Non-deterministic processes election Select process Run Update Time elapse Init (+ 1 automaton per process to reflect its state) Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 31 / 70 >

  52. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches T 1 × T 2 × T 3 × Sch T 1 × T 2 × T 3 Synchronous automata Asynchronous automata + scheduler Dedicated product SystemC Concurrent program T 1 × T 2 × T 3 T 1 × T 2 × T 3 × Sch Asynchronous product Asynchronous automata shared variable Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

  53. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches T 1 × T 2 × T 3 × Sch T 1 × T 2 × T 3 Synchronous automata Asynchronous automata + scheduler Dedicated product SystemC Concurrent program T 1 × T 2 × T 3 T 1 × T 2 × T 3 × Sch Asynchronous product Asynchronous automata shared variable Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

  54. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches T 1 × T 2 × T 3 × Sch T 1 × T 2 × T 3 Synchronous automata Asynchronous automata + scheduler Dedicated product SystemC Concurrent program T 1 × T 2 × T 3 T 1 × T 2 × T 3 × Sch Asynchronous product Asynchronous automata shared variable Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

  55. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches T 1 × T 2 × T 3 × Sch T 1 × T 2 × T 3 Synchronous automata Asynchronous automata + scheduler Dedicated product SystemC Concurrent program T 1 × T 2 × T 3 T 1 × T 2 × T 3 × Sch Asynchronous product Asynchronous automata shared variable Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

  56. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC to Spin: encoding events notify/wait for event E k : p ::notify( E k ): p ::wait( E k ): ∀ i ∈ P | W i == K W p := k W i := 0 blocked( W p == 0) W p : integer associated to process p . W p = k ⇔ “process p is waiting for event E k ”. Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 33 / 70 >

  57. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC to Spin: encoding time and events discrete time a deadline variable T p is attached to each process p T p = next execution time for process p p ::wait(d): “Set my next execution time to T p := T p + d now + d and wait until the current blocked( T p == min i ∈ P ( T i ) ) execution time reaches it” Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 34 / 70 >

  58. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC to Spin: encoding time and events discrete time a deadline variable T p is attached to each process p T p = next execution time for process p p ::wait(d): “Set my next execution time to T p := T p + d now + d and wait until the current blocked( T p == min ( T i ) ) execution time reaches it” i ∈ P W i == 0 p ::notify( E k ): p ::wait( E k ): ∀ i ∈ P | W i == K W p := K W i := 0 blocked( W p == 0) T i := T p Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 34 / 70 >

  59. SoCs and TLM Compilation Verification Extra-functional Conclusion SystemC to Spin: results 7e+06 PinaVM [SPIN 07] 6e+06 5e+06 4e+06 Nb of states 3e+06 2e+06 1e+06 0 PinaVM 2 4 6 8 10 12 14 16 18 20 22 Matthieu Moy (LIP) Transaction-Level Models of SoCs Nb of components February 2018 < 35 / 70 >

  60. SoCs and TLM Compilation Verification Extra-functional Conclusion Encoding Approaches T 1 × T 2 × T 3 × Sch T 1 × T 2 × T 3 Synchronous automata Asynchronous automata + scheduler Dedicated product SystemC Concurrent program T 1 × T 2 × T 3 T 1 × T 2 × T 3 × Sch Asynchronous product Asynchronous automata shared variable Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 36 / 70 >

  61. SoCs and TLM Compilation Verification Extra-functional Conclusion Outline Introduction: Systems-on-a-Chip, Transaction-Level Modeling 1 Compilation of SystemC/TLM 2 Verification of SystemC/TLM 3 Extra-Functional Properties in TLM 4 Conclusion 5 Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 36 / 70 >

  62. SoCs and TLM Compilation Verification Extra-functional Conclusion This section Extra-Functional Properties in TLM 4 Time and Parallelism Power and Temperature Estimation Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 36 / 70 >

  63. SoCs and TLM Compilation Verification Extra-functional Conclusion Parallelization of Simulations WIFI SPI USB A U C O M R T E R U M Ethernet PRCMU M I T E T I C CAN R ADC ADC PWM DOCSIS U T R A E R C O M U M I2C DAC T I T I M R E C DAC UART CORE MMU Audio LIN Compo Capteur H.265 TIMER ITC DISPLAY Capteur UART CORE MMU GPU TIMER ITC MEM CTLR Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 37 / 70 >

  64. SoCs and TLM Compilation Verification Extra-functional Conclusion Parallelization of Simulations System-level Simulation Vs HPC Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 38 / 70 >

  65. SoCs and TLM Compilation Verification Extra-functional Conclusion Problems and solutions for parallel execution of SystemC/TLM (1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable) Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 39 / 70 >

  66. SoCs and TLM Compilation Verification Extra-functional Conclusion Problems and solutions for parallel execution of SystemC/TLM (1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable) � No 100% automatic and efficient solution for TLM Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 39 / 70 >

  67. SoCs and TLM Compilation Verification Extra-functional Conclusion Problems and solutions for parallel execution of SystemC/TLM (1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable) � No 100% automatic and efficient solution for TLM Our proposal = additional constructs: Desynchronization (1) / Synchronization (2) Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 39 / 70 >

  68. SoCs and TLM Compilation Verification Extra-functional Conclusion Approaches to parallelization Efficient Targets a Few/no wide subset of modifications SystemC required Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 40 / 70 >

  69. SoCs and TLM Compilation Verification Extra-functional Conclusion SC - DURING : The Idea SC_THREAD_1 OS thread_1 SC_THREAD_2 OS thread_2 . . . SC_THREAD_N OS thread_ N SystemC OS thread Unmodified SystemC Some computation delegated to other threads Weak synchronization between SystemC and threads thanks to tasks with duration Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 41 / 70 >

  70. SoCs and TLM Compilation Verification Extra-functional Conclusion Simulated Time Vs Wall-Clock Time Wall-clock time Time elapse Computation 0 10 20 30 40 Simulated time Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 42 / 70 >

  71. SoCs and TLM Compilation Verification Extra-functional Conclusion Simulated Time in SystemC and SC - DURING SystemC A B sc-during P Q Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

  72. SoCs and TLM Compilation Verification Extra-functional Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // Computation SystemC A f(); // Time taken by f B wait(20); sc-during P Q Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

  73. SoCs and TLM Compilation Verification Extra-functional Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // Computation SystemC A f(); // Time taken by f B wait(20); g() Process P: wait(20) sc-during g(); P wait(20); Q Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

  74. SoCs and TLM Compilation Verification Extra-functional Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // Computation SystemC A f(); // Time taken by f B wait(20); g() Process P: wait(20) sc-during g(); h() P wait(20); during(15, h); Q Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

  75. SoCs and TLM Compilation Verification Extra-functional Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // Computation SystemC A f(); // Time taken by f B wait(20); g() Process P: wait(20) sc-during g(); h() P wait(20); during(15, h); i() j() Q Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

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