Available CDM ESD Tester Non-Socketed CDM Socketed CDM Insulator Socket Conductor Plate High-Voltage Power Supply 2007. Dec. Ryan Hsin-Chin Jiang 19 2007. Dec. 姜 信 欽
HBM / MM ESD Failure on the I/O Transistors HBM / MM ESD Failure on the I/O Transistors MM Failure HBM Failure 2007. Dec. Ryan Hsin-Chin Jiang 20 2007. Dec. 姜 信 欽
General ESD Specifications for IC Products General ESD Specifications for IC Products HBM MM CDM Basic Spec. for Commercial IC’s Okay +/- 2kV +/- 200V +/- 1kV Safe +/- 4kV +/- 400V +/- 1.5kV Super +/- 10kV +/- 1kV +/- 2kV * An IC during ESD test with all pin combinations has to pass above ESD specifications (both positive and negative ESD voltages). * ESD failure criterion including pin leakage current and all function testing. This Spec. Can’ ’t Guarantee System Level ESD Performance! t Guarantee System Level ESD Performance! This Spec. Can 2007. Dec. Ryan Hsin-Chin Jiang 21 2007. Dec. 姜 信 欽
CMOS Technology Roadmap CMOS Technology Roadmap ESD Process Silicide/ optimization Salicide Still be major Still be major HC Process optimization concern concern LDD Reliability Hot Carrier ESD ESD degradation Concerns degradation degradation Feature 3 2 1.5 1.0 0.8 0.5 0.35 0.25 0.18 Size (µm) Junction 0.8 0.5 0.4 0.35 0.3 0.25 0.2 0.18 0.15 Depth (µm) Oxide 500 400 300 200 150 100 70 50 30 Thickness (A) 2007. Dec. Ryan Hsin-Chin Jiang 22 2007. Dec. 姜 信 欽
ESD Event for Systems ESD Event for Systems (System Level) (System Level) 2007. Dec. Ryan Hsin-Chin Jiang 23 2007. Dec. 姜 信 欽
System- -Level ESD Testing Standard Level ESD Testing Standard System ♦ ♦ IEC 61000- -4 4- -2 2: Electromagnetic Compatibility (EMC) : Electromagnetic Compatibility (EMC) IEC 61000 Part 4: Testing and measurement techniques Part 4: Testing and measurement techniques Session 2: Electrostatic discharge immunity Test. Session 2: Electrostatic discharge immunity Test. 2007. Dec. Ryan Hsin-Chin Jiang 24 2007. Dec. 姜 信 欽
System- -Level ESD Gun (IEC/EN 61000 Level ESD Gun (IEC/EN 61000- -4 4- -2) 2) System Contact discharge Contact discharge head head Air discharge Air discharge head head 2007. Dec. Ryan Hsin-Chin Jiang 25 2007. Dec. 姜 信 欽
Electronics System- -Level ESD Test Set Level ESD Test Set- -up up Electronics System ♦ Test Set ♦ Test Set- -up up System is alive System is alive to be tested! to be tested! 2007. Dec. Ryan Hsin-Chin Jiang 26 2007. Dec. 姜 信 欽
System- -Level ESD Waveform Level ESD Waveform System ♦ Shortage Discharging Current Waveform ♦ Shortage Discharging Current Waveform Wide Freq. Band 2A τ (1.8 μ A/MHz) 1/ πτ 頻率 1/ π tr (10MHz) (320MHz) 2007. Dec. Ryan Hsin-Chin Jiang 27 2007. Dec. 姜 信 欽
Electronics System- -Level ESD Test Levels Level ESD Test Levels Electronics System ♦ IEC 61000 ♦ IEC 61000- -4 4- -2 Test Levels 2 Test Levels 2007. Dec. Ryan Hsin-Chin Jiang 28 2007. Dec. 姜 信 欽
The Affection of ESD on the System Operation The Affection of ESD on the System Operation Current will automatically find Current will automatically find the lowest impedance path. the lowest impedance path. The electromagnetic The electromagnetic field generated by ESD field generated by ESD Shell Shell The electromagnetic field The electromagnetic field generated by ESD generated by ESD 電場 kV/m 電場 kV/m 磁場 A/m 磁場 A/m 4 4 15 15 3 3 10 10 Hole Hole 2 2 10 cm 10 cm Bad Contact Bad Contact 1 1 20 cm 20 cm 5 5 50 cm 50 cm 時間 ns 時間 ns 5 10 15 5 10 15 2007. Dec. Ryan Hsin-Chin Jiang 29 2007. Dec. 姜 信 欽
Electronics System- -Level ESD Test Criteria Level ESD Test Criteria Electronics System Class Criterion Result More popular More popular No abnormal phenomenon Class A Pass Criterion for High Criterion for High occurs during ESD stress 。 Quality Products! Quality Products! Abnormal phenomenon Class B occurs during ESD stress, but Pass will recover automatically 。 Abnormal phenomenon Pass/ Class C occurs after ESD stress, Fail manual restart is needed 。 Hardware damage 。 Class D Fail 2007. Dec. Ryan Hsin-Chin Jiang 30 2007. Dec. 姜 信 欽
Where has to be tested and How is the test Level? Where has to be tested and How is the test Level? ♦ Test points ： All contactable points. ♦ Test Level ： Shell ： contact 8kV 。 I/O ports ： Should be also 8kV 。 Why: Why: Although the data pins in the I/O Although the data pins in the I/O ports can not be touched by hands, ports can not be touched by hands, But the 8kV ESD event can stress But the 8kV ESD event can stress the data pins via Cable Discharge Cable Discharge the data pins via method. method. 2007. Dec. Ryan Hsin-Chin Jiang 31 2007. Dec. 姜 信 欽
The informal Classification of ESD Performances The informal Classification of ESD Performances •Class 1 equipment (2 Class 1 equipment (2 kv kv test level) should test level) should: : • - Not be in a low humidity environment Not be in a low humidity environment - - be protected by Anti be protected by Anti- -static Material static Material - •Class 2 equipment (4 Class 2 equipment (4 kv kv test level) should : test level) should : • - be protected by Anti be protected by Anti- -static Material static Material - •Class 3 equipment (8 Class 3 equipment (8 kv kv test level) should : test level) should : • - be in a low humidity environment be in a low humidity environment - •Class 4 equipment (15 Class 4 equipment (15 kv kv test level) should : test level) should : • - Not to worry (too much) Not to worry (too much) - 2007. Dec. Ryan Hsin-Chin Jiang 32 2007. Dec. 姜 信 欽
Cable Discharging Event Cable Discharging Event (CDE) (CDE) (New Focused Event) (New Focused Event) 2007. Dec. Ryan Hsin-Chin Jiang 33 2007. Dec. 姜 信 欽
Cable Discharge Event Cable Discharge Event ♦ Tribocharging (surface charges) Cable frictionizes with floor. ♦ Tribocharging (space charges) Cable carries high voltage signal. ♦ Tribocharging (space charges) Cable is placed in electric field ♦ Induced voltages If a cable is subjected by the field of a strong pulse (e.g., a lightning stroke, ESD close to the cable) a momentary voltage will be introduced along the cable. 2007. Dec. Ryan Hsin-Chin Jiang 34 2007. Dec. 姜 信 欽
IEEE 802.3 Cable Discharge Ad- -Hoc Hoc IEEE 802.3 Cable Discharge Ad • Direct Pin Injection Contact Direct Pin Injection Contact • Discharge Test is necessary for is necessary for Discharge Test evaluating the immunity to Cable the immunity to Cable evaluating Discharge Event! ! Discharge Event 2007. Dec. Ryan Hsin-Chin Jiang 35 2007. Dec. 姜 信 欽
Direct Pin Injection Contact Discharge Test Direct Pin Injection Contact Discharge Test 2007. Dec. Ryan Hsin-Chin Jiang 36 2007. Dec. 姜 信 欽
The References for Cable Discharge Events The References for Cable Discharge Events 1. K. Chatty, P. Cottrell, R. Gauthier, M. Muhammad, F. Stellari Stellari, A. , A. Weger Weger, P. Song, and M. McManus, , P. Song, and M. McManus, 1. K. Chatty, P. Cottrell, R. Gauthier, M. Muhammad, F. “Model “ Model- -based guidelines to suppress cable discharge event (CDE) induced based guidelines to suppress cable discharge event (CDE) induced Latchup Latchup in CMOS ICs, in CMOS ICs,” ” in Proc. IEEE International Reliability Physics Symp in Proc. IEEE International Reliability Physics Symp., 2004, pp.130 ., 2004, pp.130- -134. 134. 2. 2. R. Brooks, “ R. Brooks, “A simple model for a cable discharge event, A simple model for a cable discharge event,” ” IEEE 802.3 Cable Discharge Ad IEEE 802.3 Cable Discharge Ad- -hoc, hoc, March 2001. (http://www.ieee802.org/3/ad_hoc/copperdis/public/docs/cable_discharge_model1.pdf). March 2001. 3. 3. J. Deatherage J. Deatherage and D. Jones, and D. Jones, “ “Multiple factors trigger cable discharge events in Multiple factors trigger cable discharge events in ethernet ethernet LANs, LANs,” ” Electronic Design, vol. 48, no. 25, pp. 111- -116, Dec., 2000. (http:// 116, Dec., 2000. (http://www.elecdesign www.elecdesign. . Electronic Design, vol. 48, no. 25, pp. 111 com/Articles/ArticleID/4991/4991.html). com/Articles/ArticleID/4991/4991.html). 4. Intel Corporation, “ “Cable discharge event in local area network environment, Cable discharge event in local area network environment,” ” White Paper, Order White Paper, Order 4. Intel Corporation, No: 249812- No: 249812 -001, July 2001. 001, July 2001. 5. “Cabling ESD Study, Cabling ESD Study,” ” IEEE 802.3 Cable Discharge Ad IEEE 802.3 Cable Discharge Ad- -hoc, March 2001. (http://www. hoc, March 2001. (http://www. 5. “ ieee802.org/3/ad_hoc/copperdis/ public/docs/index.html ieee802.org/3/ad_hoc/copperdis/ public/docs/ index.html). ). 6. 6. Telecommunications Industry Association (TIA), Category 6 Cabling: Static Discharge Between Telecommunications Industry Association (TIA), Category 6 Cablin g: Static Discharge Between LAN Cabling and Data Terminal Equipment, Category 6 Consortium, Dec. 2002. LAN Cabling and Data Terminal Equipment, Category 6 Consortium, Dec. 2002. 7. 7. H. Geski H. Geski, , “ “DVI compliant ESD protection to IEC 61000 DVI compliant ESD protection to IEC 61000- -4 2 level d Standard, 4 2 level d Standard,” ” in Conformity, Sept. in Conformity, Sept. 2004, pp. 12- -17. 17. 2004, pp. 12 8. 8. T.- T. -H. Lai and M. H. Lai and M.- -D. D. Ker Ker, , “ “Method to evaluate cable discharge event (CDE) reliability of in Method to evaluate cable discharge event (CDE) reliability of integrated tegrated circuits in CMOS technology,” ” in Proc. of IEEE International Symposium on Quality Electronic in Proc. of IEEE International Symposium on Quality Electronic circuits in CMOS technology, Design, 2006, pp. 597- -602. 602. Design, 2006, pp. 597 9. M.- -D. D. Ker Ker and T. and T.- -H. Lai, H. Lai, “ “Dependence of layout parameters on CDE (cable discharge event) Dependence of layout parameters on CDE (cable discharge event) 9. M. robustness of CMOS devices in a 0.25- -mm mm salicided salicided CMOS process, CMOS process,” ” in Proc. of IEEE International in Proc. of IEEE International robustness of CMOS devices in a 0.25 Reliability Physics Symp Reliability Physics Symp., 2006, pp.633 ., 2006, pp.633- -634. 634. 2007. Dec. Ryan Hsin-Chin Jiang 37 2007. Dec. 姜 信 欽
Two Field Return Cases Two Field Return Cases 2007. Dec. Ryan Hsin-Chin Jiang 38 2007. Dec. 姜 信 欽
A Field Return Case A Field Return Case Hot plug on/off, chip IO diode damaged C=0.1uF signal connector R=75 ohm damaged PCB Chip IO Chip passed HBM 2kV, Chip passed HBM 2kV, MM 200V test MM 200V test This case tells two things: This case tells two things: 1. Component level performance can Component level performance can’ ’t guarantee System level performance. t guarantee System level performance. 1. 2. Cable Discharge Event exists practically. Cable Discharge Event exists practically. 2. 2007. Dec. Ryan Hsin-Chin Jiang 39 2007. Dec. 姜 信 欽
System Level ESD Protector Is Necessary System Level ESD Protector Is Necessary Hot plug on/off, chip IO diode damaged C=0.1uF signal connector R=75 ohm damaged PCB Chip IO System Level ESD Protector System Level ESD Protector Chip passed HBM 2kV, Chip passed HBM 2kV, should be placed at here! should be placed at here! MM 200V test MM 200V test 2007. Dec. Ryan Hsin-Chin Jiang 40 2007. Dec. 姜 信 欽
Another Field Return Case Another Field Return Case • Chip passed Chip passed Latchup Latchup test, but test, but Latchup Latchup still happened after still happened after • System Level ESD test. So called . So called Transient Transient Latchup Latchup Issue Issue. . System Level ESD test SCR path stays at ON. SCR path stays at ON. 2007. Dec. Ryan Hsin-Chin Jiang 41 2007. Dec. 姜 信 欽
System Level ESD Protector Is Necessary System Level ESD Protector Is Necessary Shell Shell Transient Voltage passes to VDD trace on PCB Transient Voltage passes to VDD trace on PCB VDD VDD ESD Protector ESD Protector IC IC GND GND Necessary! Necessary! PCB PCB 2007. Dec. Ryan Hsin-Chin Jiang 42 2007. Dec. 姜 信 欽
Two Regions on a System Need ESD Protectors Two Regions on a System Need ESD Protectors I/O ports I/O ports Critical Critical Power/Control/Signal Power/Control/Signal Lines Lines 2007. Dec. Ryan Hsin-Chin Jiang 43 2007. Dec. 姜 信 欽
EFT Event for Systems EFT Event for Systems (System Level) (System Level) 2007. Dec. Ryan Hsin-Chin Jiang 44 2007. Dec. 姜 信 欽
EFT Event EFT Event ♦ ♦ Electrical Fast Transients (EFT) occur as a result of arcing contacts in tacts in Electrical Fast Transients (EFT) occur as a result of arcing con switched and relays. switched and relays. ♦ ♦ EFT disturbances are common in industrial environments where EFT disturbances are common in industrial environments where electromechanical switches are used to connect and disconnect electromechanical switches are used to connect and disconnect inductive loads. . inductive loads ♦ ♦ IEC 61000 IEC 61000- -4 4- -4 4 specifies the EFT threat in both specifies the EFT threat in both power power and and I/O data lines I/O data lines. . ♦ EFT Burst ♦ EFT Burst 2007. Dec. Ryan Hsin-Chin Jiang 45 2007. Dec. 姜 信 欽
EFT COUPLING CLAMP EFT COUPLING CLAMP 2007. Dec. Ryan Hsin-Chin Jiang 46 2007. Dec. 姜 信 欽
IEC 61000- -4 4- -4 EFT Severity Level 4 EFT Severity Level IEC 61000 ♦ Level ♦ Level- -1 : In Well Protected Environment 1 : In Well Protected Environment ♦ Level ♦ Level- -2 : In Protected Environment 2 : In Protected Environment ♦ Level ♦ Level- -3 : In Typical Industrial Environment 3 : In Typical Industrial Environment ♦ Level ♦ Level- -4 : In Severe Industrial Environment 4 : In Severe Industrial Environment ♦ ♦ Like ESD, EFT can be fatal Like ESD, EFT can be fatal on data and I/O lines. on data and I/O lines. ♦ ♦ Protectors are needed. Protectors are needed. 2007. Dec. Ryan Hsin-Chin Jiang 47 2007. Dec. 姜 信 欽
EFT Test Criteria EFT Test Criteria Class Criterion Result No abnormal phenomenon occurs Class A Pass during EFT stress 。 Abnormal phenomenon occurs Class B during EFT stress, but will recover Pass automatically 。 Abnormal phenomenon occurs after Class C EFT stress, manual restart is Fail needed 。 Hardware damage 。 Class D Fail 2007. Dec. Ryan Hsin-Chin Jiang 48 2007. Dec. 姜 信 欽
Surge Event for Systems Surge Event for Systems (System Level) (System Level) 2007. Dec. Ryan Hsin-Chin Jiang 49 2007. Dec. 姜 信 欽
Surge Event Surge Event ♦ ♦ IEC 61000- -4 4- -5 5 addresses addresses the most severe transient conditions the most severe transient conditions on both on both IEC 61000 power and data lines. power and data lines. ♦ ♦ These are transient caused by lightning strikes lightning strikes and and switching. switching. These are transient caused by ♦ ♦ Switching transients may be the result of power switching, load changes may be the result of power switching, load changes Switching transients in power distribution systems, or short circuit fault conditions. . in power distribution systems, or short circuit fault conditions ♦ ♦ Lightning transients may result from a direct strike or induced voltages Lightning transients may result from a direct strike or induced voltages and current due to an indirect strike. and current due to an indirect strike. Voltage Pulse Current Pulse Voltage Pulse Current Pulse so called 1.2/50us waveform so called 8/20us waveform so called 1.2/50us waveform so called 8/20us waveform 2007. Dec. Ryan Hsin-Chin Jiang 50 2007. Dec. 姜 信 欽
IEC 61000- -4 4- -5 Surge Severity Level 5 Surge Severity Level IEC 61000 Unbalanced Lines Data Bus Power Supply Balanced Lines (Long Distance Bus) (Short Distance Bus) Class Coupling Mode Coupling Mode Coupling Mode Coupling Mode Line to Line Line to Earth Line to Line Line to Earth Line to Earth Line to Earth (Zs=2 Ω ) (Zs=12 Ω ) (Zs=42 Ω ) (Zs=42 Ω ) (Zs=42 Ω ) (Zs=42 Ω ) 0 Current (A) NA NA NA NA NA NA 1 Current (A) NA 42 NA 12 12 NA 2 Current (A) 250 84 12 24 24 12 3 Current (A) 500 167 24 48 48 NA 4 Current (A) 1000 333 48 96 48 NA 5 Current (A) Note Note 48 96 96 NA Note: Depends on the class of the local power supply system. 0: Well protected environment; 1: Partially protected environment; 0: Well protected environment; 1: Partially protected environmen t; 2: Well separated cables; 3: Cables run in parallel; 2: Well separated cables; 3: Cables run in parallel; 4: Multi- -wire cables for both electronic & electrical circuits; wire cables for both electronic & electrical circuits; 4: Multi 5: Connection to telecommunications cables and overhead power lines nes 5: Connection to telecommunications cables and overhead power li 2007. Dec. Ryan Hsin-Chin Jiang 51 2007. Dec. 姜 信 欽
Surge Test Criteria Surge Test Criteria Class Criterion Result No abnormal phenomenon occurs Class A Pass during Lightning stress 。 Abnormal phenomenon occurs Class B during Lightning stress, but will Pass recover automatically 。 Abnormal phenomenon occurs after Class C Lightning stress, manual restart is Fail needed 。 Hardware damage 。 Class D Fail 2007. Dec. Ryan Hsin-Chin Jiang 52 2007. Dec. 姜 信 欽
One Region on a System Need EFT/Surge Protectors One Region on a System Need EFT/Surge Protectors Power, I/O ports Power, I/O ports 2007. Dec. Ryan Hsin-Chin Jiang 53 2007. Dec. 姜 信 欽
The Functions of Transient The Functions of Transient Voltage Suppressor (TVS) Voltage Suppressor (TVS) (System Level ESD Protection Devices) (System Level ESD Protection Devices) 2007. Dec. Ryan Hsin-Chin Jiang 54 2007. Dec. 姜 信 欽
The Function of ESD Protection Device The Function of ESD Protection Device I/O port of a Product I/O port of a Product ♦ ♦ Prevent the operation of an Electronic Product from the Prevent the operation of an Electronic Product from the � Bypass the ESD current - � disturbance of ESD event. - Bypass the ESD current disturbance of ESD event. and and Clamp the voltage at a low value. Clamp the voltage at a low value. 2007. Dec. Ryan Hsin-Chin Jiang 55 2007. Dec. 姜 信 欽
The Operation of TVS Device The Operation of TVS Device System mal- System mal -function threshold function threshold Prevent System from Malfunction! Prevent System from Malfunction! TVS’ ’s s Clamping Voltage Clamping Voltage is the most important parameter. is the most important parameter. TVS Different Systems have different “ “system mal system mal- -function threshold function threshold” ” values. values. Different Systems have different 2007. Dec. Ryan Hsin-Chin Jiang 56 2007. Dec. 姜 信 欽
How to Evaluate the Protection Performance of TVS Device ? How to Evaluate the Protection Performance of TVS Device ? See See Clamping Voltage during bypassing the transient Its Clamping Voltage during bypassing the transient Its ESD current ! ESD current ! Lower Clamping Voltage, Higher Protection Performance ! Lower Clamping Voltage, Higher Protection Performance ! 2007. Dec. Ryan Hsin-Chin Jiang 57 2007. Dec. 姜 信 欽
TVS’ ’s s Clamping Voltage Clamping Voltage TVS ESD Current waveform ESD Current waveform For ESD event: For ESD event: During TVS is bypassing ESD current, During TVS is bypassing ESD current, High freq. High freq. its terminal voltage is the ESD Clamping its terminal voltage is the ESD Clamping 。 Voltage 。 Voltage Lower Clamping Voltage means greater Lower Clamping Voltage means greater ESD protection performance. ESD protection performance. For Lightning event: For Lightning event: During TVS is bypassing Lightning current, During TVS is bypassing Lightning current, its terminal voltage is the Lightning its terminal voltage is the Lightning Low freq. Low freq. 。 Clamping Voltage 。 Clamping Voltage Lightning Current waveform Lightning Current waveform Lower Clamping Voltage means greater Lower Clamping Voltage means greater Lightning protection performance. Lightning protection performance. 2007. Dec. Ryan Hsin-Chin Jiang 58 2007. Dec. 姜 信 欽
How to Measure the Clamping Voltage of TVS Device ? (I) How to Measure the Clamping Voltage of TVS Device ? (I) Not Proper ! Not Proper ! 2007. Dec. Ryan Hsin-Chin Jiang 59 2007. Dec. 姜 信 欽
How to Measure the Clamping Voltage of TVS Device ? (II) How to Measure the Clamping Voltage of TVS Device ? (II) The Proper The Proper Method: Method: Transmission Transmission Line Pulsing (TLP) Line Pulsing (TLP) System System 2007. Dec. Ryan Hsin-Chin Jiang 60 2007. Dec. 姜 信 欽
How to Measure the TVS TVS’ ’s s ESD Clamping Voltage? (III) ESD Clamping Voltage? (III) How to Measure the TVS’ TVS ’s s ESD Clamping Voltage Only can be measured by using TLP measurem ESD Clamping Voltage Only can be measured by using TLP measurement ent system. Because ESD is a high freq. noise, measuring this high freq waveform req waveform system. Because ESD is a high freq. noise, measuring this high f 。 needs to do the impedance matching 。 needs to do the impedance matching 30ns~100ns （ （ similar to ESD Gun similar to ESD Gun’ ’s waveform s waveform ） ） 30ns~100ns I_TLP E E D I_TLP D C C + B DUT V_TLP B A A - V_TLP t The Clamping Voltage during Bypassing ESD ♦ TLP: Transmission Line Pulsing. ♦ TLP: Transmission Line Pulsing. Current (I_TLP). 2007. Dec. Ryan Hsin-Chin Jiang 61 2007. Dec. 姜 信 欽
An Example of TLP I- -V Curve V Curve An Example of TLP I ♦ When I ♦ Transmission Line Pulsing (TLP) Measurement When I TLP =I ESD = 16A (~ESD TLP =I ESD = 16A (~ESD 20 5kV), the TVS 5kV), the TVS’ ’s s ESD clamping ESD clamping 18 voltage V CL voltage V CL = 12V. = 12V. 16 V_pulse ♦ When I ♦ 14 When I TLP TLP =I =I ESD ESD = 6A (~ESD = 6A (~ESD Pulse from a transmission line 12 2kV), the TVS TVS’ ’s s ESD clamping ESD clamping 2kV), the TLP_I 100ns + 10 voltage V CL = 8.75V. voltage V CL = 8.75V. TLP_V DUT 8 - 6 4 I/O to GND 2 0 0 2 4 6 8 10 12 14 Transmission Line Pulsing (TLP) Voltage (V) 2007. Dec. Ryan Hsin-Chin Jiang 62 2007. Dec. 姜 信 欽
Clamping Voltage Comparison by TLP Measurement Clamping Voltage Comparison by TLP Measurement TLP: Transmission Line Pulsing TLP: Transmission Line Pulsing Sx Sx x x x x x x x x x x x x 04S -04S S S Pxxxxxx Pxxxxxx AZ1015- AZ1015 Cxxx Cxxx Stress condition: Stress condition: I/O vs. GND I/O vs. GND 2007. Dec. Ryan Hsin-Chin Jiang 63 2007. Dec. 姜 信 欽
TLP Clamping Voltage Determines the System ESD Performance TLP Clamping Voltage Determines the System ESD Performance Put ESD Protect IC Put ESD Protect IC @ USB Port @ USB Port Contact Discharge @ USB ports of PCB Contact Discharge @ USB ports of PCB (Class- (Class -A) A) Self Recover Errors Self Recover Errors ( X: error happened, V: pass)) ( X: error happened, V: pass)) ± 600V ± 1kV ± 2kV ± 4kV Parts Parts ± 600V ± 1kV ± 2kV ± 4kV (contact) (contact) (contact) (contact) (contact) (contact) (contact) (contact) X --- --- --- Cxxxx Cxxxx X --- --- --- Pxxxxxx X --- --- --- Pxxxxxx X --- --- --- Sx V V X --- Sx V V X --- AZ1015- -04S 04S V V V V AZ1015 V V V V 2007. Dec. Ryan Hsin-Chin Jiang 64 2007. Dec. 姜 信 欽
The Clamping Types of TVS Devices The Clamping Types of TVS Devices Unipolar Unipolar gnd Bipolar Bipolar gnd 2007. Dec. Ryan Hsin-Chin Jiang 65 2007. Dec. 姜 信 欽
TVS’ ’s s Lightning Clamping Voltage Measurement Lightning Clamping Voltage Measurement TVS TVS’ ’s s Lightning (8us/20us) Clamping Voltage can be measured by using Lightning (8us/20us) Clamping Voltage can be measured by using TVS oscilloscope. This is because Lightning pulse (<1MHz) is a low freq req oscilloscope. This is because Lightning pulse (<1MHz) is a low f noise. noise. GND GND 2007. Dec. Ryan Hsin-Chin Jiang 66 2007. Dec. 姜 信 欽
TVS’ ’s s Peak Pulse Power (to Lightning Waveform, 8/20us) Peak Pulse Power (to Lightning Waveform, 8/20us) TVS TVS’ ’s s Peak Pulse Power Peak Pulse Power ： ： TVS P pk P pk = = I I pp pp x x V V clamp clamp ： 。 I pp pp ： the max. lightning Current that TVS can bypass 。 I the max. lightning Current that TVS can bypass ： V clamp clamp ： the terminal voltage during TVS is bypassing the max. lightning V the terminal voltage during TVS is bypassing the max. lightning Current. Current. TVS’ ’s s Peak Pulse Power is Not an important parameter. It Peak Pulse Power is Not an important parameter. It TVS easily makes users choose wrong TVS. easily makes users choose wrong TVS. ： For example ： For example TVS- -1 : 1 : Ipp Ipp =12 A, =12 A, Vclamp Vclamp = 8V, Power = V*I =96W = 8V, Power = V*I =96W TVS TVS- -2 : 2 : Ipp Ipp = 12A, = 12A, Vclamp Vclamp = 20V, Power = V*I =240W = 20V, Power = V*I =240W TVS Do you think which one has better protection performance? Do you think which one has better protection performance? Answer is the TVS- -1, which 1, which Vclamp Vclamp is lower. is lower. Answer is the TVS If you use Power as your selection criterion, you will choose TVS S- -2! But, 2! But, If you use Power as your selection criterion, you will choose TV its protection performance is poor than that of TVS- -1. 1. its protection performance is poor than that of TVS 2007. Dec. Ryan Hsin-Chin Jiang 67 2007. Dec. 姜 信 欽
The TVS Arrays The TVS Arrays 2007. Dec. Ryan Hsin-Chin Jiang 68 2007. Dec. 姜 信 欽
The Types of ESD Protection devices The Types of ESD Protection devices ♦ Transient Voltage Suppressors (TVS) ♦ Transient Voltage Suppressors (TVS) ♦ Varistor ♦ Varistor ♦ Zener ♦ Zener diode diode ♦ Diode ♦ Diode ♦ The main function of TVS is to absorb high peak power as a surge ♦ The main function of TVS is to absorb high peak power as a surge device. device. ♦ ♦ It also can be an ESD protector. It also can be an ESD protector. ♦ ♦ Advantages Advantages Single channel, 2 terminals, easy to use. Single channel, 2 terminals, easy to use. Cheap. Cheap. ♦ ♦ Disadvantages Disadvantages Clamping Voltage is high. Clamping Voltage is high. C load is big, not suitable for high speed C load is big, not suitable for high speed application. application. 2007. Dec. Ryan Hsin-Chin Jiang 69 2007. Dec. 姜 信 欽
The Types of ESD Protection devices (cont’ ’d) d) The Types of ESD Protection devices (cont ♦ Integrated ESD protection array ♦ Integrated ESD protection array ♦ Zener ♦ Zener diode array diode array ♦ Regular Diodes array ♦ Regular Diodes array ♦ Special designed array ♦ Special designed array ♦ ♦ Advantages Advantages Multiple channels. Multiple channels. Small size. Small size. C load could be low, suitable for high C load could be low, suitable for high speed applications. speed applications. ♦ ♦ Disadvantages Disadvantages Cost is a little of higher than TVS. Cost is a little of higher than TVS. Board has to be pre- Board has to be pre -designed for use. designed for use. 2007. Dec. Ryan Hsin-Chin Jiang 70 2007. Dec. 姜 信 欽
Application Examples of TVS Diodes Array Application Examples of TVS Diodes Array Varistors TVS Arrays Varistors TVS Arrays TVS Arrays TVS Arrays Diodes Diodes ♦ Save Board Area! ♦ Save Board Area! ♦ Save Total System Cost! ♦ Save Total System Cost! 2007. Dec. Ryan Hsin-Chin Jiang 71 2007. Dec. 姜 信 欽
Varistor, TVS Diode, and TVS Diode Array , TVS Diode, and TVS Diode Array Varistor Varistor TVS Diode TVS Diode Array Response Time Slow Fast Fast Clamp Voltage High Low Low Peak ESD Current High Lower, but Enough Lower, but Enough C_load High Medium Low Heat Sink Good Fare Fare Individual Cost Low Low High System Cost High High Low 2007. Dec. Ryan Hsin-Chin Jiang 72 2007. Dec. 姜 信 欽
The Types of TVS arrays The Types of TVS arrays ♦ Steering Diode Design ♦ Steering Diode Design ♦ C_load ♦ C_load should be small : Should not affect the should be small : Should not affect the VDD High Speed Data transmission. High Speed Data transmission. ♦ Clamping Voltage ♦ Clamping Voltage should be small : Lower should be small : Lower High Speed I/O Bus I/O value can sustain higher ESD level. value can sustain higher ESD level. C_load Transmission Line Pulsing (TLP) Measurement Transmission Line Pulsing (TLP) Current (A) 20 GND 18 Clamping Voltage Clamping Voltage 16 V_pulse 14 Pulse from a 12 transmission line TLP_I 100ns + 10 TLP_V DUT 8 - 6 For High Speed I/O port For High Speed I/O port 4 I/O to GND 2 VDD 0 VDD 0 2 4 6 8 10 12 14 Transmission Line Pulsing (TLP) Voltage (V) ESD Current VDD IC to be protected Keyboard data-1 Connector Terminal Printer data-2 . I/O I/O . Control-1 . GND ESD Current 1 2 1 2 AZ2015-02S AZ2015-02S GND GND 3 3 For Low Speed I/O port For Low Speed I/O port 2007. Dec. Ryan Hsin-Chin Jiang 73 2007. Dec. 姜 信 欽
The Installation considerations of TVS Devices (Ground Issue Ground Issue) ) The Installation considerations of TVS Devices ( ♦ TVS solution ♦ TVS solution ♦ Mechanical solution ♦ Mechanical solution ESD Bad! Bad! Chassis Chassis OR OR Chassis Chassis It costs. It costs. Wrong Wrong ESD Good! Good! Shield 正確 正確 Design a discharge path Design a discharge path 2007. Dec. Ryan Hsin-Chin Jiang 74 2007. Dec. 姜 信 欽
The Installation considerations of TVS Devices The Installation considerations of TVS Devices ♦ The trace inductance plays a key role. ♦ Core Circuit Region The trace inductance plays a key role. small small large large Small VDD or I/O's Small IC / ASIC small small TVS I/O Ports I/O Ports Signal Ground L1 - L1 - between the connector and the ESD suppressor, between the connector and the ESD suppressor, smaller is better to reduce smaller is better to reduce the possibility of transient signal coupling to sensitive traces or power plates! or power plates! the possibility of transient signal coupling to sensitive traces L2 - - between the ESD suppressor and the I/O pin of the chip , between the ESD suppressor and the I/O pin of the chip , bigger is better to bigger is better to L2 reduce the transient voltage amplitude which is seen at IC/ASIC side! side! reduce the transient voltage amplitude which is seen at IC/ASIC L3 - - between the I/O line and the ESD suppressor (stub trace), between the I/O line and the ESD suppressor (stub trace), smaller is better to smaller is better to L3 let the potential of signal trace be the same as the clamping voltage of TVS! ltage of TVS! let the potential of signal trace be the same as the clamping vo 2007. Dec. Ryan Hsin-Chin Jiang 75 2007. Dec. 姜 信 欽
The Application Examples of The Application Examples of TVS Arrays TVS Arrays 2007. Dec. Ryan Hsin-Chin Jiang 76 2007. Dec. 姜 信 欽
Computer Systems Computer Systems Card Reader South Bridge Audio North Bridge CPU USB 2.0 10M/100M/ 1G LAN IEEE 1394 PS2 Print Port DVI VGA HDMI SATA 2007. Dec. Ryan Hsin-Chin Jiang 77 2007. Dec. 姜 信 欽
LCD Display Systems LCD Display Systems 2007. Dec. Ryan Hsin-Chin Jiang 78 2007. Dec. 姜 信 欽
Portable Systems Portable Systems Mic LED Speaker Ext. Memory LCD Card Interface Keypad Volumn Adj/ ON/OFF Battery Serial Port USB/OTG 2007. Dec. Ryan Hsin-Chin Jiang 79 2007. Dec. 姜 信 欽
TVS Array Helps USB ports to pass 2~8KV contact Mode Class- -A Criterion A Criterion TVS Array Helps USB ports to pass 2~8KV contact Mode Class I/O 4 VDD I/O 3 Typical Variation of CIN vs. VIN 6 5 4 4.0 Can pass 2.0 eye Can pass 2.0 eye 3.5 Input Capacitance (pF) 3.0 AZ1015- -04S 04S AZ1015 2.5 2.0 (SOT23- -6L) 6L) (SOT23 1.5 1.0 VDD = 5V, GND = 0V, f = 1MHz, T=25 oC, 0.5 1 2 3 0.0 I/O 1 GND I/O 2 0 1 2 3 4 5 Input Voltage (V) Clamping Voltage vs. Peak Pulse Current Transmission Line Pulsing (TLP) Measurement Transmission Line Pulsing (TLP) Current (A) 15 20 Lowest Value Lowest Value 14 Lowest Value Lowest Value 18 13 12 16 Clamping Voltage (V) 11 V_pulse 14 10 Pulse from a transmission line 9 12 TLP_I 8 100ns + 10 For Lightning For Lightning 7 TLP_V DUT 6 8 - 5 6 Waveform 4 Parameters: For ESD For ESD 3 4 tr=8 μ s I/O pin to GND pin I/O to GND 2 td=20 μ s 2 1 0 0 4 5 6 7 8 9 10 11 12 13 0 2 4 6 8 10 12 14 Peak pulse Current (A) Transmission Line Pulsing (TLP) Voltage (V) 2007. Dec. Ryan Hsin-Chin Jiang 80 2007. Dec. 姜 信 欽
TVS Array on USB ports TVS Array on USB ports V BUS V BUS 1. VDD pin directly short to USB’ ’s VBUS s VBUS 1. VDD pin directly short to USB R T D+ plate, No trace connection. plate, No trace connection. USB R T D _ Port1 2. 2. GND pin directly short to USB’ GND pin directly short to USB ’s GND s GND C T C T plate, No trace connection. plate, No trace connection. 6 5 4 USB GND Controller AZ1015-04S 3. TVS can NOT be placed at the 3. TVS can NOT be placed at the V BUS 1 2 3 boundary of different power Plates. boundary of different power Plates. C T C T D+ 4. Data trace should be connected to 4. Data trace should be connected to USB R T D _ Port2 TVS’ TVS ’s s I/O pin first, then connected to I/O pin first, then connected to R T the controller. the controller. GND GND That’ ’s ALL! s ALL! That GND GND Common Mode Choke GND GND 3 1 D1- D2- Amazing's 6-pin TVS D1+ D2+ 4 6 USBV USBV Common Mode Choke Chip cap. Use power plate GND GND is better Dual Ports USB Connector 2007. Dec. Ryan Hsin-Chin Jiang 81 2007. Dec. 姜 信 欽
TVS Array Helps USB ports to pass 2~8KV contact Mode Class- -A Criterion A Criterion TVS Array Helps USB ports to pass 2~8KV contact Mode Class USB 2.0 Eye Diagram Measurement Result USB 2.0 Eye Diagram Measurement Result @ High Speed Operation Mode @ High Speed Operation Mode Port 1 Port 2 Port 3 Port 4 Port 1 Port 2 Port 3 Port 4 w/o w/o ESD Device ESD Device w/ w/ TVS TVS (AZ1015- -04S) 04S) (AZ1015 2007. Dec. Ryan Hsin-Chin Jiang 82 2007. Dec. 姜 信 欽
Choose Different TVS TVS’ ’s s Specs for Different ESD Test Specs. Specs for Different ESD Test Specs. Choose Different I/O 4 VDD I/O 3 Lower Price Lower Price 6 5 4 ♦ AZC099 ♦ AZC099- -04S 04S ♦ AZC002 ♦ AZC002- -04S 04S 1 2 3 ♦ AZC015 ♦ AZC015- -04S 04S I/O 1 GND I/O 2 SOT23-6L ♦ AZ1015 ♦ AZ1015- -04S 04S Simple ESD Design Flow: ♦ AZ1045 Simple ESD Design Flow: ♦ AZ1045- -04S 04S Pick & Place! Pick & Place! Higher ESD spec. Higher ESD spec. & Higher Criterion & Higher Criterion 2007. Dec. Ryan Hsin-Chin Jiang 83 2007. Dec. 姜 信 欽
TVS Arrays on VGA port (for 3kV ~ 8kV contact ESD) TVS Arrays on VGA port (for 3kV ~ 8kV contact ESD) Green VCC Red VCC VCC 1 6 6 5 4 AZ1015-04S GND Red Video VDD Red 2 5 Filter 3 4 75 Ω Green Green Signals From Scaler Video Blue Green Red Blue Filter 1 75 Ω 5 VSYNC 1 2 3 Blue Video HSYNC Blue Filter * optional 75 Ω 0.1uF or 0.01uF DDC_Data 15 11 chip capacitor for filtering DDC_CLK high-frequency ESD noise VCC VSYNC V-Sync H-Sync DDC DA T VCC DDC CLK DDC_CLK VSYNC 6 5 4 FB DIG_GND HSYNC FB 1 6 AZ1015-04S Red_GND GND DDC_Data VDD 2 5 FB Green_GND 3 4 DDC_CLK FB Blue_GND 1 2 3 HSYNC DDC_Data GND 15-pin VGA connector Lower Price Lower Price ♦ AZC099 ♦ AZC099- -04S 04S ♦ AZC002 ♦ AZC002- -04S 04S Pick & Pick & ♦ AZC015 ♦ AZC015- -04S 04S Place! Place! ♦ AZ1015 ♦ AZ1015- -04S 04S ♦ AZ1045 ♦ AZ1045- -04S 04S Higher ESD spec. Higher ESD spec. & Higher Criterion. & Higher Criterion. TVS arrays TVS arrays 2007. Dec. Ryan Hsin-Chin Jiang 84 2007. Dec. 姜 信 欽
TVS Arrays on DVI port (for 3kV ~ 8kV contact ESD) TVS Arrays on DVI port (for 3kV ~ 8kV contact ESD) VCC common mode TMDS_D2+ TMDS_D2- VCC choke 1 2 6 5 4 TMDS-D2- VCC TMDS-D2+ 3 4 CKT CKT 24 24 TMDS_D2- common mode choke 1 2 TMDS_D2+ TMDS-D1- 1 2 3 Signals From Scaler TMDS-D1+ TMDS_D1- 3 4 TMDS_D1+ TMDS_D1- CKT1 CKT1 TMDS_D0+ TMDS_D0- TMDS_D1+ common mode VCC choke VCC * optional 1 2 TMDS-D0- 6 5 4 0.1uF or 0.01uF TMDS_D0- chip capacitor for filtering TMDS-D1+ high-frequency ESD noise 3 4 TMDS_D0+ 0.1uF 0.1uF common mode choke TMDS_CK- 1 2 TMDS-CK- 0.1uF 0.1uF 0.1uF 0.1uF 1 2 3 TMDS_CK+ TMDS-CK+ 3 4 TMDS_CK- AZC099-04S AZC099-04S AZC099-04S AZC099-04S AZC099-04S AZC099-04S TMDS_CK+ DDC_CLK DDC_CLK DDC_Data VCC DDC_CLK FB VCC DDC_Data DDC_Data 6 5 4 FB Detect TMDS DATA CLK- TMDS DATA CLK- TMDS DATA CLK+ TMDS DATA CLK+ Hot Plug Detect Hot Plug Detect DDC DATA DDC DATA DDC CLK DDC CLK +5V Power +5V Power TMDS DATA 2+ TMDS DATA 2+ TMDS DATA 2- TMDS DATA 2- TMDS DATA 1+ TMDS DATA 1+ TMDS DATA 1- TMDS DATA 1- TMDS DATA 0+ TMDS DATA 0+ TMDS DATA 0- TMDS DATA 0- Detect FB GND 1 2 3 DVI_D connector Detect Lower Price ♦ AZC099 Lower Price ♦ AZC099- -04S 04S TVS arrays TVS arrays ♦ AZC002 ♦ AZC002- -04S 04S Pick & Pick & ♦ AZC015 ♦ AZC015- -04S 04S Place! Place! ♦ AZ1015 ♦ AZ1015- -04S 04S ♦ AZ1045 ♦ AZ1045- -04S 04S Higher ESD spec. Higher ESD spec. & Higher Criterion. & Higher Criterion. 2007. Dec. Ryan Hsin-Chin Jiang 85 2007. Dec. 姜 信 欽
HDMI Block Diagram HDMI Block Diagram ♦ ♦ Audio, video and auxiliary data is transmitted across the three TMDS data channels. TMDS data channels. Audio, video and auxiliary data is transmitted across the three ♦ ♦ A TMDS clock is transmitted on the TMDS clock channel and is used by the receiver as a d by the receiver as a A TMDS clock is transmitted on the TMDS clock channel and is use frequency reference for data recovery on the three TMDS data channels. nnels. frequency reference for data recovery on the three TMDS data cha ♦ ♦ The DDC is used by the Source to read the Sink’ ’s Enhanced Extended Display s Enhanced Extended Display The DDC is used by the Source to read the Sink Identification Data (E- -EDID) in order to discover the Sink EDID) in order to discover the Sink’ ’s configuration and/or s configuration and/or Identification Data (E capabilities. capabilities. 2007. Dec. Ryan Hsin-Chin Jiang 86 2007. Dec. 姜 信 欽
Conceptual Schematic for one TMDS differential pair Conceptual Schematic for one TMDS differential pair ♦ ♦ The termination resistance (RT) and the characteristic The termination resistance (RT) and the characteristic impedance of the cable (Z0) must be matched! must be matched! impedance of the cable (Z0) 2007. Dec. Ryan Hsin-Chin Jiang 87 2007. Dec. 姜 信 欽
The Problems of Adding TVS on TMDS differential pairs The Problems of Adding TVS on TMDS differential pairs 、 The 1 、 The C_load C_load of TVS will destroy the impedance match. of TVS will destroy the impedance match. 1 、 The termination resistance will induce back drive current. 2 、 The termination resistance will induce back drive current. 2 Power OFF = 0V Power ON = 5V Backdrive Current TVS TVS HDMI Source HDMI Sink 2007. Dec. Ryan Hsin-Chin Jiang 88 2007. Dec. 姜 信 欽
The Solutions to Make Impedance Match The Solutions to Make Impedance Match 、 Do trace compensation to add inductance. 1 、 Do trace compensation to add inductance. 1 ♦ The trace width may ♦ The trace width may become very small if become very small if C (TVS) is larger than C (TVS) is larger than 1pF. 1pF. 、 Make the 2 、 Make the C_load C_load of TVS to of TVS to approach 0.5pF approach 0.5pF , or below. , or below. 2 Such C_load C_load will have will have small influence small influence on impedance on impedance Such match. No trace compensation is needed No trace compensation is needed. . match. 2007. Dec. Ryan Hsin-Chin Jiang 89 2007. Dec. 姜 信 欽
TVS Arrays Help HDMI port to pass 8KV contact Mode TVS Arrays Help HDMI port to pass 8KV contact Mode I/O 4 I/O 3 GND Transmission Line Pulsing (TLP) Measurement 18 6 5 4 Power- -Rail Rail Power 16 14 V_pulse 12 Pulse from a transmission line TLP_I 10 100ns + TLP_V DUT 8 - 6 4 Lowest Value Lowest Value VDD to GND 2 1.0 1 2 3 0 0.9 AZ1045- -04S 04S AZ1045 I/O- -to to- -GND GND 0 1 2 3 4 5 6 7 8 9 10 I/O I/O 1 VDD I/O 2 0.8 Transmission Line Pulsing (TLP) Voltage (V) Capacitance (pF) 0.7 AZ1045- -04S 04S AZ1045 0.55pF 0.55pF Transmission Line Pulsing (TLP) Measurement 0.6 18 (SOT23- -6L) 6L) (SOT23 0.5 I/O- I/O -to to- -GND GND 16 0.4 14 0.3 V_pulse Lowest Value Lowest Value 12 Pulse from a 0.2 transmission line TLP_I 10 100ns + 0.1 TLP_V DUT 8 - 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 6 Lowest Value Lowest Value Voltage (V) 4 I/O to GND 2 0 0 2 4 6 8 10 12 14 Transmission Line Pulsing (TLP) Voltage (V) 2007. Dec. Ryan Hsin-Chin Jiang 90 2007. Dec. 姜 信 欽
TVS Arrays on HDMI port (1) TVS Arrays on HDMI port (1) TMDS_D2+ TMDS_D2+ Via hole to GND TMDS_D2- GND TMDS_GND 3 2 1 TMDS_D2- AZ1045-04SU TMDS_D1+ 4 5 6 +5V TMDS_D1+ TMDS_GND Via hole to +5V Via hole to GND TMDS_D1- C=100nF TMDS_D1- (optional) TMDS_D0+ TMDS_D0+ Via hole to GND TMDS_GND TMDS_D0- GND 3 2 1 TMDS_D0- AZ1045-04SU TMDS_CK+ 4 5 6 TMDS_GND TMDS_CK+ +5V Via hole to +5V TMDS_CK- Via hole to GND C=100nF TMDS_CK- (optional) CE_REMOTE CE_REMOTE Via hole to GND N/C DDC_CLK GND 3 2 1 DDC_CLK AZC099-04S DDC_DAT 4 5 6 GND DDC_DAT +5V Via hole to +5V +5V OUT Via hole to GND C=100nF HOTPLUG_DET (optional) HOTPLUG_DET HDMI Connector 2007. Dec. Ryan Hsin-Chin Jiang 91 2007. Dec. 姜 信 欽
TVS Arrays on HDMI port (2) TVS Arrays on HDMI port (2) NC 1 10 Line-1 AZ1045- AZ1045 -04Q 04Q (MSOP- -10L) 10L) (MSOP NC 2 9 Line-2 GND 3 VDD 8 NC 4 7 Line-3 NC 5 Line-4 6 TMDS_D2+ TMDS_D2+ 1 10 TMDS_D2- 2 9 TMDS_GND C=100nF (optional) 3 GND +5V 8 TMDS_D2- 4 7 TMDS_D1+ TMDS_D1+ 5 6 TMDS_D1- TMDS_GND TMDS_D1- TMDS_D0+ TMDS_D0+ 1 10 TMDS_D0- 2 9 TMDS_GND C=100nF (optional) 3 GND +5V 8 TMDS_D0- 4 7 TMDS_CK+ TMDS_CK+ 5 6 TMDS_CK- TMDS_GND TMDS_CK- CE_REMOTE CE_REMOTE Via hole to GND N/C DDC_CLK GND 3 2 1 DDC_CLK AZC099-04S DDC_DAT 4 5 6 GND VCC DDC_DAT Via hole to VCC +5V IN Via hole to GND C=100nF HOTPLUG_DET (optional) HOTPLUG_DET HDMI Connector Flow through layout style. Flow through layout style. 2007. Dec. Ryan Hsin-Chin Jiang 92 2007. Dec. 姜 信 欽
(Examples) TVS Arrays for Low Speed I/O Ports (Examples) TVS Arrays for Low Speed I/O Ports AZ2015- -02S 02S AZ2015- -01H/01L 01H/01L AZ2015 AZ2015- -04C/04S 04C/04S AZ2015- -05C/05S 05C/05S AZ2015 AZ2015 AZ2015 (SOT23- -3L) 3L) (SOD523, SOD323) (SOT23 (SOT353, SOT23- -5L) 5L) (SOT363, SOT23- -6L) 6L) (SOD523, SOD323) (SOT353, SOT23 (SOT363, SOT23 GND 6 4 5 4 5 1 3 1 2 3 1 2 2 1 2 3 I/O I/O 3 1 AZ2025- -01H (SOD523) 01H (SOD523) AZ2025- -02S 02S AZ2025 AZ2025 AZ2025- -01L(SOD323) 01L(SOD323) (SOT23- -3L) 3L) AZ2025 (SOT23 2 1 2 2007. Dec. Ryan Hsin-Chin Jiang 93 2007. Dec. 姜 信 欽
Choosing Low Clamping Voltage TVS Arrays Choosing Low Clamping Voltage TVS Arrays ♦ Excellent Clamping Performance ♦ Excellent Clamping Performance ♦ The Lower Clamping Voltage ♦ The Lower Clamping Voltage @ 8/20us Current @ 8/20us Current helps systems to pass Higher helps systems to pass Higher ESD level with Class- -A criteria. A criteria. ESD level with Class Lowest Value is the best choice. is the best choice. Lowest Value AZ2015- -02S 02S AZ2015 @ TLP Current @ TLP Current 17 AZ2015-02S I/O vs. G ND 16 AZ2015-02S I/O vs. I/O 15 14 TLP pulse width : 100ns 13 12 11 Pulse rise/fall time: 1ns/1ns Current (A) 10 9 8 7 6 Lowest Value is the best choice. is the best choice. Lowest Value 5 4 AZ2015- AZ2015 -02S 02S 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Voltage (V) 2007. Dec. Ryan Hsin-Chin Jiang 94 2007. Dec. 姜 信 欽
Bidirectional Clamping TVS Arrays Bidirectional Clamping TVS Arrays @ Bidirectional node @ Bidirectional node AUR Input Output AUL Shield V BR V CL 1 1 Transient gnd gnd Voltage -V BR -V CL 2 2 V BR Normal gnd gnd Operation AUR -V BR AUL Shield Protected 1 2 Devices 1 2 3 Audio Port Audio Port 3 2007. Dec. Ryan Hsin-Chin Jiang 95 2007. Dec. 姜 信 欽
TVS Arrays on Low Speed I/O Ports / Internal Buses TVS Arrays on Low Speed I/O Ports / Internal Buses VDD IC to be protected I/O 1 IC to be protected Keyboard data-1 Connector Terminal I/O 2 Printer Connector data-2 . . I/O 3 Control-1 . GND I/O 4 GND 1 2 1 2 5 4 AZ2015-02S AZ2015-02S 3 3 1 2 3 Low Speed I/O port Low Speed I/O port Low Speed I/O port Low Speed I/O port Low Speed I/O port Low Speed I/O port I/O 1 IC to be protected I/O 2 VDD Connector VCC I/O 3 Low Speed Control Line I/O 4 Data Line Chip-B I/O 5 Chip-A Low Speed Control Line GND Data Line 6 5 4 Chip-C AZ2015-02S 1 2 3 AZ2015-02S AZ2015-02S GND Low Speed Low Speed Low Speed Low Speed Low Speed I/O port Low Speed I/O port Internal Buses Internal Buses Internal Buses Internal Buses 2007. Dec. Ryan Hsin-Chin Jiang 96 2007. Dec. 姜 信 欽
TVS Arrays on Low Speed I/O Ports / Internal Buses TVS Arrays on Low Speed I/O Ports / Internal Buses ♦ Mobile Phone Application (pass 12kV Air ESD) ♦ Mobile Phone Application (pass 12kV Air ESD) AZ2015- -05C 05C AZ2015 (SOT363) (SOT363) 6 5 4 TVS arrays on TVS arrays on Internal Buses Internal Buses 1 2 3 TVS arrays on Low TVS arrays on Low Speed I/O Port Speed I/O Port 2007. Dec. Ryan Hsin-Chin Jiang 97 2007. Dec. 姜 信 欽
TVS Arrays on Critical Internal Buses TVS Arrays on Critical Internal Buses ♦ LCM Module for Mobile Products (pass 12kV Air ESD) ♦ LCM Module for Mobile Products (pass 12kV Air ESD) AZ2015- -01H 01H AZ2015 (SOD523) (SOD523) 1 TVS TVS 2 TVS TVS TVS TVS 2007. Dec. Ryan Hsin-Chin Jiang 98 2007. Dec. 姜 信 欽
TVS Arrays on Ground Plates Connections TVS Arrays on Ground Plates Connections ♦ ♦ Shielding GND should be Shielding GND should be ♦ ♦ Shielding GND should be shorted Shielding GND should be shorted shorted to Chassis. shorted to Chassis. to Chassis. to Chassis. ♦ ♦ Each GND plate should be short Each GND plate should be short together via ferrobead ferrobead and and TVS TVS’ ’s s together via ♦ ♦ Each power plate should has its Each power plate should has its own TVS connected to GND own TVS connected to GND 2007. Dec. Ryan Hsin-Chin Jiang 99 2007. Dec. 姜 信 欽
100 Ryan Hsin-Chin Jiang 欽 信 姜 2007. Dec. 2007. Dec. Summary Summary
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