The Flat Panel Display Paradigm: Successful Implementation of Microelectronic Processes on Gigantic Wafers Dr. Zvi Yaniv Applied Nanotech, I nc. 3006 Longhorn Blvd., Suite 107 Austin, TX 78758 Phone 512-339-5020 x103 Fax 512-339-5021 Email zyaniv@appliednanotech.net
Flat Panel Displays (FPD) 2007 Active Matrix Liquid Crystal (AMLCD) FPD Plasma (PDP) Active Matrix Organic Light Emitting Diodes (AMOLED) Field Emission (FED)
Samsung PDP Ken Werner (Nutmeg Consultants)
Sharp AMLCD Ken Werner (Nutmeg Consultants)
LG Philips LTPS AMOLED 20.1” Ken Werner (Nutmeg Consultants)
Predictions… Once FPDs have achieved comparable size and performance to CRTs, … FALLING PRICE PREMIUM FPD UNIT PRICE CRT ? 1990 2000 2010 YEAR American Electronics Association (1990)
Predictions …, their intrinsic advantages will result in penetration constrained only by their relative price premium versus CRTs ...AND INCREASING SCREEN SIZE... 50- CRT 40- MAXIMUM SCREEN SIZE 30- (INCHES) FPD 20- 10- 1990 2000 2010 YEAR 0- American Electronics Association (1990)
Solids, Liquids and Gases - It’s all About Order No Glasses I sotropic Liquids Gases O Long-Range R Order D E Mesomorphic Glasses Liquid Crystals R Less Than (Mesomorphic —————— I 3-D Long Fluids) Plastic Crystals N Range G Order 3-D Crystalline Solids Long Range Order Definite Shape Definite Volume Complete And Volume Only Mobility MOBI LI TY
Liquid Crystal?! Flat Panel Display Technology, Solid State Technology, 1994
Twisted Nematic (TN) Structure The molecules along the upper plate point in direction ‘a’ and those along the lower pate in direction ‘b’, thus forcing the liquid crystals into an overall twisted state.
Why LC Active Matrix Displays are Necessary? � Need of Time-Multiplexed Matrix Addressing � For passive displays (such as LCDs) time multiplexing has inherent limitations
Principals of Operation of a TFT AMLCD • t p – scanning pulse length liquid crystal resistivity ≈ 10 12 Ω -cm • • storage time ≈ 20 msec • polarity of the applied voltage must be inverted periodically: • reversing the data voltage polarity in each frame • reversing the data voltage polarity on alternative rows
Energy Band Diagram of Crystalline and Amorphous Silicon ENERGY ENERGY 1.75 eV 1.1 eV DENSITY OF STATES DENSITY OF STATES
Plasma Vapor Deposition RF OR DC POWER ~ .1 WATT/CM 2 PRESSURE ~ 1 TORR GAS GAS EXHAUST PLASMA FEED SUBSTRATE HEATER TEMP ~ 250 °C FEED GAS MATERIAL SiH 4 , SiF 4 , H 2 α - Si (INTRINSIC) (+ B 2 H 6 ) α - Si (p-TYPE) (+ PH 3 ) α - Si (n-TYPE) SiH 4 +N 2 O SiO 2 SiH 4 + NH 3 Si 3 N 4
Cross-Section of TFT Pixel Array with Storage Capacitor
Projected Limitations of α -Si TFT AMLCD’s Based on Predicted Technological Improvements 10 8 Lithography Resolution (mm –1 ) 6 Transistor Performance 4 Gate Delay 2 0 0 5 10 15 20 25 30 35 40 Diagonal (in)
AMLCD Process Flow 1 2 4 Active Plate 3 3 4 3 Completed Cell Display 1 3 4 Display Passive Plate Functional In-Process Test 1 Optical Pattern In-Process Inspection 2 Panel Inspection 3 Repair 4
Pixel Layout Example ( α -Si TFT)
Example of Clean Room Layout YELLOW ROOM WET ROOM Exp | Coater / Developer Wet Etching Stations Exp | Coater / Developer Exp | Coater / Developer Exp | Coater / Developer Resist Removal Stations Exp | Coater / Developer Exp | Coater / Developer Cleaning Stations Dry Etcher CVD CVD Sputtering Dry Etcher CVD CVD Sputtering Dry Etcher CVD Dry Etcher Sputtering Sputtering
Cluster Tool Configuration s s e c Process o r P r e b m Chamber a h C Process Heating Chamber Chamber Transportation Robot LD/UL L U / D L Transportation Robot Cassette Station
Block Diagram of TFT-LCD Module
LSI Driver Connection to TCP (tape-carrier package) by ACF
From GEN 1 to GEN 7
Display Size & Pixel Density for Large Screen Screen Size 40” 1280x768 1280x768 30” 1920x1200 24” XGA .8M pixels SXGA 1.5 M 1280x1024 UXGA 1.9 M 17” D-TV 1M/2M 1024x768 15” WUXGA 2.3M 1M 2M 4M 5M Pixel Contents
Yield Depend on Screen Size and Pixel Contents
First Generation 7 α -Si
Display Cost 0.26 TFT Plate 0.42 Lighting Color Filter Plate 0.14 Drive 0.18
Comparison of Various Silicon Films
Major Crystallization Methods
Industry Transition to Polysilicon Material Applications High Single Crystal Silicon —— x-Si Wafers Integrated Circuits Electrical Performance (Semiconductors) Polysilicon* —— p-Si (Mobility) Pixels + Integrated Thin Films Circuits Microcrystalline Silicon —— m-Si Amorphous Silicon —— a-Si Pixels Only Low * Crystallization converts a-Si or m-Si to p-Si
Wide Viewing Technologies
The Old Dream of Hang on the Wall TV is Here Today Courtesy of Information Display Magazine
The Old Dream of Hang on the Wall TV is Here Today Courtesy of Information Display Magazine
What is “Plasma” Shigeo Mikoshiba, SID Seminars
Where Does the Light Come From? Shigeo Mikoshiba, SID Seminars
Cross Section of Fundamental Color PDP Structure
Sandblasting Method
Barrier Ribs Made with the Sandblasting Method – Rib Pitch: 130 µm
Negative Features of PDPs � Low luminance (400 cd/m 2 ) � Low contrast ratio (20:1 in bright room) � Low luminous efficiency (1.4 lm/W) � High drive voltage
OLED Displays
OLEDs Need an “Active Matrix” Shown is a simplified cross-sectional view of a full-color solution- processed OLED device structure.
Ink Jet Processing?
LTPS vs. α -Si as Materials for AMOLED TFTs α -Si TFT LTPS TFT 50-200 0.5-1 Mobility (cm 2 / V-sec) PMOS and NMOS NMOS Type of TFT Worse Better TFT Uniformity 9 or 10 masks 4 or 5 masks Number of Process Steps High Low Cost (array only) Low (Built-in Driver) High (External Driver) Cost (modile) High Low Equipment I nvestment Low High Yield Lower for small panel sizes Lower for large panel size Overall Cost High Low Current Stability Much less sensitive Much more sensitive OLED Degradation
The Competing Powers for Large Area FPDs
LCD vs Plasma vs OLEDs
Target for ultra-high definition and wide screen display F. Sato and M. Seki, I DW ’01, p.1153
Cross-section of FED in operation Light Anode Glass Black Matrix Phosphor Electrons Grid Conducting Insulating Grid Cathode Feedlines Spacer Layer Glass
SCE Display Schematic cross section of the construction in the SCE display.
PdO fabrication process Schematic diagram of the PdO fabrication process by using ink jet printing.
SED demo
Glass vs Silicon Information Display Magazine, 11/05
1995 Lithography Requirements � Minimum Feature Size: 2µm - 5µm � Linewidth Control: +10% � Layer-to-Layer Overlay: +0.5µm - +1µm � Throughput: >10 x 10 6 mm 2 per hour � Typical Products: TVs, Computer Terminals, CAD Workstations, Auto Dashboards, Image sensors & Scanners, Print Heads MRS Technology Inc.
Coating Technology � Spin Coating � Roller Coating � Spray Coating � Slot Coating
Lithography Systems � Contact / Proximity Aligners � Mirror Projection Aligners � Step-and-Repeat Aligners
Schematic of a Scanning Projection Aligner & Schematic of a Stitching Aligner Flat Panel Display Technology, Solid State Technology, 1994
Stepping Aligners � Available Systems are ‘Adapted’ IC Steppers � Advantages � Multiple Suppliers � Resolution, Overlay: Sub-Micron Available � High Defect Limited Yield � Use Standard IC Masks Available from Multiple Suppliers � High Throughput for Small Displays � Problems � Limitations of Projection Optics Constrain Display Size � No Migration Path to Large Displays MRS Technology Inc.
The Stitching Aligner The Job: Make a display of any arbitrary size by stitching � together multiple subfields. Analogous to making a brick wall out of individual bricks. Problem #1: Doing it � The ‘mortar joints’ between the ‘bricks’ must be invisible! � Many kinds of ‘bricks’ are used! � Problem #2: Doing it Fast! � Many exposures, mask changes needed to pattern a single display � layer Slow = Expensive = Prototype Displays � Fast = Inexpensive = Production Displays � Problem #3: Doing it Easily � Multiple subfield stitching jobs are complex � Need to know what you get is what you want � MRS Technology Inc.
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