The Design of SNAP2 National ASIC Design Engineering Center, - PowerPoint PPT Presentation

The Design of SNAP2 National ASIC Design Engineering Center, Institute of Automation, Chinese Academy of Sciences Presenter: Qiuxiang Fan Email: qiuxiang.fan@ia.ac.cn 1

Outline  Introduction  Powerful FPGA  High-Speed Interface  Mezzanine Card  Structure  Development flow  New board  Our team

SNAP2  XCKU115-FLVF1924 FPGA  XCKU115-FLVF1924 FPGA  Zynq XC7Z010  Zynq XC7Z010  4xQDRII  4xQDRII  2xDDR3  2xDDR3  4xQSFP connectors  4xQSFP connectors  2 Ethernet PHY interface with RJ-  2 Ethernet PHY interface with RJ- 45 connectors 45 connectors  2xFMC HPC connectors  2xFMC HPC connectors  4xZD+ connectors  4xZD+ connectors  3xSMA: clock/1pps/trigger  3xSMA: clock/1pps/trigger  Micro secure digital (SD)  Micro secure digital (SD) connector connector  2xQuad spi flash  2xQuad spi flash  Usb interface  Usb interface

SNAP2 SIZE:233X160mm SIZE:233X160mm (6U standard) (6U standard) Mechanical Dimension of Snap2 Mechanical Dimension of Snap2

Powerful FPGA KU115:  Highest transceiver bandwith  Highest DSP count  Highest on- chip memory available

Powerful Interface  10/40GE(QSFP)  PCIe(QSFP)  RapidIO(QSFP)  JESD204B  HMC

 Connect to10/40G Ethernet switch  Connect to RapidIO switch

Board design • (1)High-speed PCB material TU-872 SLK SP • (2)Excellent PCB stack(20 layers) • (3) Adequate power supply design(V CCINT current up to 50A)

Board design • (4)Strict skew constraints for high-speed differential pairs(Differential pairs<=2mil,Relative propagation delay<=10mil, ) • (5)Optimize the via of high-speed signal(back-drill 、 anti-pad) • (6)High-speed signal integrity test(eye-pattern 、 jitter 、 bit-error- rate)

Powerful Mezzanine Card(FMC)——ADC •ADC8x250-8 • ADC1x3200-12 •ADC8x250-8 • ADC1x3200-12  2x Hittite HMCAD1520 8bit ADC  1x TI ADC12D1600 12bit ADC  2x Hittite HMCAD1520 8bit ADC  1x TI ADC12D1600 12bit ADC  8 inputs, 250 MSPS@8 bits  2 inputs, 1.6 Gsps  8 inputs, 250 MSPS@8 bits  2 inputs, 1.6 Gsps  4 inputs, 500 MSPS @8 bits  1 inputs, 3.2 Gsps  4 inputs, 500 MSPS @8 bits  1 inputs, 3.2 Gsps  2 inputs, 1000 MSPS @8 bits  2 inputs, 1000 MSPS @8 bits •ADC1x5000-10 •ADC1x5000-10  1x e2V EV10AQ190 10bit ADC •ADC8x250-14  1x e2V EV10AQ190 10bit ADC •ADC8x250-14  4 inputs,1.25 Gsps  4x TI ADS62P49 14bit ADC  4 inputs,1.25 Gsps  4x TI ADS62P49 14bit ADC  2 inputs, 2.5 Gsps  8 inputs, 250 MSPS@14 bits  2 inputs, 2.5 Gsps  8 inputs, 250 MSPS@14 bits  1 inputs, 5 Gsps  1 inputs, 5 Gsps (1)ADC1x3200-12 (2)ADC1x5000-10 (3)ADC8x250-8 (4)ADC8x250-14 (1)ADC1x3200-12 (2)ADC1x5000-10 (3)ADC8x250-8 (4)ADC8x250-14

Powerful Mezzanine Card(FMC)——40/100GE&DAC (2)DAC1x5500-12 (1)2x40GE module  2xQSFP+ connector  1x Euvis MD657B 12bit DAC  up to 5.5 Gsps rate

Structure  Snap2 plugged in 1U cabinet

Structure  Snap2 plugged in 9U cabinet

Development Flow FPGA and Zynq Configuration The configuration circuit of Snap2 system is highly flexible: 1.User can configure the FPGA and Zynq through JTAG respectively for development and debug; 2.Both FPGA and Zynq have a Quad SPI flash for configuration. After power up, FPGA and Zynq can load or boot themselves automatically from Quad SPI flash; 3.User can reconfigure FPGA through the Ethernet port connected to FPGA; 4.User can reconfigure Zynq through the Ethernet port connected to Zynq; 5.Zynq can configure FPGA through the SelectMAP interface of FPGA.

Development Flow Flexible work mode: 1)Zynq as system controller  Zynq configure FPGA through selectMAP interface of FPGA  Zynq send commands to FPGA and receive responses from FPGA through SPI bus  The modules in FPGA integrated by AXI4 on-chip bus

Development Flow 2) Microblaze as system controller  The modules in FPGA integrated by AXI and Wishbone on-chip bus  Support JASPER tool flow

Based on Simulink Development Environment Based on Simulink Development Environment Correlator PFB FFT Correlator PFB FFT

Control software System bootload control System bootload control High speed Interface Information High speed Interface Information Power voltage & Board temperature information Power voltage & Original AD data display Board temperature information Original AD data display Current information Current information

Our new board  Size ： standard 6U,233mm X 160mm X 2mm  Zynq AP Soc XC7Z010 based system controller  UltraScale+ FPGA XCVU13P- 2IFHGA2104 is used for high-speed operation and high-speed interconnect ： compatibility with Virtex UltraScale+ XCVU9P- 2IFLGA2104 • Eight 8Gb DDR4 component memories • Two 144Mb QDR component memories • A 2Gb serial peripheral interface flash memory (Quad SPI) is used to configure FPGA • Four zQSFP+(QSFP28) connectors and cages • Two VITA 57.1 FMC HPC connectors • Three ZD+ backplane connector 。 • Two Ethernet PHY interface with RJ-45 connectors • Some SMA connectors. The input trigger signal, external clock and 1pps signal are from SMA connectors

FPGA resource

layout

Our team(staff) Jie Hao Jingbin Mu Leichen Zhou Liangtian Zhao Qiuxiang Fan Lin Shu Dou Wang Meiting Zhao Hui Feng Zhifeng Lv Yafang Song Yuting Li Sai Ma Chengcheng Li

Thank you! Email: qiuxiang.fan@ia.ac.cn 2 3