Testing of the DHE Modules Dima Levit, Paolo Di Giglio Physik Department E18 - Technische Universität München The 19th International Workshop on DEPFET Detectors and Applications May 12nd, 2015. Kloster Seeon supported by: Maier-Leibnitz-Labor der TU und LMU München, Cluster of Excellence: Origin and Structure of the Universe, BMBF Belle
Tests at CAD-UL Tests at TUM DHE v.3 Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 2/16
Tests at CAD-UL Tests at TUM Outline Tests at CAD-UL Tests at TUM High Speed Links Current Source Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 3/16
Tests at CAD-UL Tests at TUM Hardware Setup at CAD-UL 52 (Belle II) and 18 (Photon Factory) DHE/DHC modules v.3.2 are produced and are tested by the board manufacturer (CAD-UL GmbH). Tests started on the January 28th. Hardware Setup Carrier board High Speed Data Generator Hameg 4040 four channel power ... 15x6.25 Gb/s supply over optical fi bers 4x1.52 Gb/s over In fi niband/optical fi bers A nettop PC with test software Clock DDR3 DHP Data Synthesizer Flash Generator Unit under Test Commissioning Problem Ethernet/IPBus Ethernet/IPBus Low FPGA core voltage (0.5 V PC instead of 1 V) wrong feedback resistance for DC/DC converter Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 4/16
Tests at CAD-UL Tests at TUM Test Environment at CAD-UL Test environment based on python scripts and standard DHH programs mostly automated, power supplies controlled by the script results stored in log files and paper check lists implemented return values in clock synthesizer and flash programmer: return != 0 - fail should be used in PXD slow control state machines Time for test: 5 min / module Tested items: IPBus Ethernet link : used for configuration and reading test results. OK . Flash programming : return value of the program, revision check. OK . Clock synthesizer : return value of the program. OK . DDR3 memory : test core with error counter. 0 errors . Power consumption : OK . Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 5/16
Tests at CAD-UL Tests at TUM Outline Tests at CAD-UL Tests at TUM High Speed Links Current Source Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 6/16
Tests at CAD-UL Tests at TUM Test Environment at TUM Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 7/16
Tests at CAD-UL Tests at TUM Test Environment at TUM Results 4 DHP high speed links : One module has link established, 1.52 Gb/s aurora with error while eyeamplitude stays at 0 counter and signal eye DFEEYEAMPLITUDE is not a good amplitude, BER up to parameter to monitor 6 . 8 · 10 − 13 Unstable aurora channels on some Current source : coarse test cards with resistive load Test repeated with IBERT (Internal (10.1 kOhm) installed on Bit-Error Rate) core adapter board Current source problems: offset current varies between cards Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 8/16
Tests at CAD-UL Tests at TUM Results. DHP Links 10 minutes test with IBERT, same parameters as with aurora links Worst case link: 500 errors Problem identified: automatic calibration of the decision feedback equalizer (DFE) Xilinx recommends to switch DFE calibration to the manual mode for 8b/10b signal (Answer Record #45483) New tests without automatic DFE calibration: all channels OK previous link with 500 errors: 0 errors over 4 days (BER < 2 · 10 − 15 ) Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 9/16
Tests at CAD-UL Tests at TUM Results. Current Source ADC:DAC, Module 0021 ADC:DAC, Module 0062 ADC ADC 4000 4000 3500 3500 3000 3000 2500 2500 2000 2000 1500 1500 1000 1000 500 500 0 0 0 10000 20000 30000 40000 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000 DAC DAC Offset current differs from module to module Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 10/16
Tests at CAD-UL Tests at TUM Current Source Schematics DCD_MON DCD_SCK DCD_SDI ADCin DCD_MON DCD_SDO DCD_CS0 U24 DCD_CS1 2 6 IN+ DOUT 3 GND IN- R167 0 U25 5 CS/SHDN 1 8 7 NC TP CLK 2 7 +5V VIN NC R168 3 6 DACVref 1 NC VOUT VREF C265 4 5 DNI GND NC 100nF C266 C267 8 4 +2.7V VDD VSS ADR4525BRZ 2.2uF 100nF C268 MCP3201 100n GND GND GND GND GND U26 DCD_SCK 8 4 DACout SCLK VOUT DCD_SDI 1 DIN High reverse current at DCD_CS0 7 3 SYNC VREF 5 AGND 2 6 +5V VDD DACGND protection diode C269 ADI-AD5060-RJ-8 100nF GND GND Problem fixed by Vout replacing the component +5V 5 U27 ERA6ARW103P 7 with the diode with lower AD8276 R169 R177 2 10k GND 0 6 0.05%, 0805, ± 10ppm/°C VtoI 3 reverse current C274 1 100nF 4 +5V GND GND 8 VloadSense DCD_CURMON_P U28 2 AD8607AR (SOIC) D14 OA2out 1 C275 PMEG2500CT 3 DHP_SENSE_VCC 100nF 6 R178 GND 7 2.2 R170 0 5 4 GND Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 11/16
Tests at CAD-UL Tests at TUM Results. Current Source Offset Current vs Gain Offset Current vs Gain 4 Gain, nA/DAC Gain, nA/DAC 3.95 3.835 3.9 3.85 3.83 3.8 3.825 3.75 3.82 3.7 3.65 3.815 3.6 − − − − 15 20 25 30 35 0.8 0.6 0.4 0.2 0 0.2 Offset Current, uA Offset Current, uA Figure : Gain fit with old diodes Figure : Gain fit with new diodes Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 12/16
Tests at CAD-UL Tests at TUM Results. Current Source Offset Current vs Gain Offset Current vs Gain 4 Gain, nA/DAC Gain, nA/DAC 3.95 3.835 3.9 3.83 3.85 3.8 3.825 3.75 3.82 3.7 3.65 3.815 3.6 − − − − 15 20 25 30 35 0.8 0.6 0.4 0.2 0 0.2 Offset Current, uA Offset Current, uA Figure : Gain fit with old diodes Figure : Gain fit with new diodes Offset Current vs Gain Gain, nA/DAC 4 3.95 3.9 3.85 3.8 3.75 3.7 3.65 3.6 0 5 10 15 20 25 30 35 40 Offset Current, uA Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 12/16
Tests at CAD-UL Tests at TUM Summary Full test and characterization of the 52 DHE modules (Belle 2): all good Basic test of the 18 DHE modules(Photon Factory) at CAD-UL: all good Variable offset current on current sources solved by replacing protection diode with lower reverse current Problem with DFE on the DHPT high speed links found. No problems caused by hardware. Next firmware update will address this issue. Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 13/16
Tests at CAD-UL Tests at TUM Thank you for your attention! Questions? Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 14/16
Tests at CAD-UL Tests at TUM Back Up Back up slides Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 15/16
Tests at CAD-UL Tests at TUM Back Up Outer Backward Outer Forward DCD1 DCD2 DCD3 DCD4 DHP1 DHP2 DHP3 DHP4 Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 16/16
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