System-on-Chip Design Analysis of Control Data Flow Hao Zheng Comp - PowerPoint PPT Presentation

System-on-Chip Design Analysis of Control Data Flow Hao Zheng Comp Sci & Eng U of South Florida 1

Overview • DF models describe concurrent computa=on at a very high level – Each actor describes non-trivial computa=on. • Each actor is oBen described in C. – Can be mapped to either HW or SW • Will look at issues in mapping C to HW. 2

Data & Control Edges of C Programs • C is used as a modeling as well as an implementa=on language. • Mapping C programs to HW is hard. – HW is parallel while C is sequen=al. – need to understand the structure of C programs. • Rela=ons between opera=ons in C programs – Data edges : data moved from one op. to another. – Control edge : no data xfer. 3

Control Flow Graph Control Edges 1 int x(a, b) { int r; int max(int a, b) 1 2 if (a > b) 3 r = a; 2 if (a > b) else 4 r = b; 3 4 r = a r = b 5 return r; } 5 return r; Control edges are oBen labeled with condi=ons whose sa=sfac=on dictates if a control can be taken. 4

Data Flow Graph Data Edges 1 int max(int a, b) { 1 int r; 2 if (a > b) a, b a 3 r = a; b 2 else (a>b) 4 r = b; 3 4 5 return r; r r } 5 Data edges are labeled with variables upon which one opera=on depends on another 5

Implemen@ng Control/Data Edges • A data edge => flow of informa=on – Must be implemented. • A control edge => result of seman=cs of program language – Maybe ignore or changed if the behavior remains the same. 6

Implemen@ng Control/Data Edges Control Edges Data Edges Hardware Implementation 1 1 a b c int sum(int a, b, c) { a, b int v1; 2 v1 = a + b; // op 2 2 c adder v2 = v1 + c; // op 3 v1 v1 return v2; adder 3 3 } v2 v2 4 4 Control edges are meaningless as HW is parallel. 7

Control/Data Edges – Example int sum(int a, b, c, d) {// op 1 int v1; v1 = a + b; // op 2 v2 = c + d; // op 3 return v1 + v2; // op 4 } 8

Basic Elements of CFG entry 1 2 3 for (i=0; i < 20; i++) { 1 // body of the loop } 2 3 exit body 9

Construc@on of CFG 1 if (a < b) { // true branch } else { // false branch } entry 1 true false exit 10

Construc@on of CFG 1 while (a < b) { // loop body } entry 1 exit body 11

Construc@on of CFG do { // loop body } while (a<b) 1 entry body 1 exit 12

Construc@on of CFG: GCD 1 1: int gcd( int a, int b) { 2: while (a != b) { 3: if (a > b) 2 6 4: a = a - b; else 5: b = b - a; 3 } 6: return a; 4 5 } A control path in CFG corresponds to a sequence of execu=ons of statements 13

Construc@on of DFG: GCD 1: int gcd( int a, int b) { 2: while (a != b) { 3: if (a > b) 1 4: a = a - b; else a, b 5: b = b - a; } 2 6 6: return a; } (a!=b) 1 3 (a>b) 2 6 a CFG 4 5 3 b 4 5 Par=al DFG 14

Construc@on of DFG: GCD 1 a a, b 1: int gcd( int a, int b) { 6 2: while (a != b) { 2 a, b 3: if (a > b) a, b a, b 4: a = a - b; a else 3 5: b = b - a; b } b a 6: return a; a b } 4 5 b a a 15

Construc@on of CFG/DFG 1 2a 1: int L[3] = {10, 20, 30}; 2c 2b 2a exit 2b 2: for (int i=1; i<3; i++) 3: L[i] = L[i] + L[i-1]; 3 How to treat indexed variables in DFG construc=on? 2c CFG 16

Construc@on of CFG/DFG a b 2a 2a i i i i i 2b 1 2b 1 L L[0], L[1], L[2] i i i 2c 2c 3 3 i i L L[1] Loca=ons of L are treated Treat L as a single individually monolithic variable 17

Construc@on of CFG/DFG a b 2a 2a i i i i i 2b 1 2b 1 L L[0], L[1], L[2] i i i 2c 2c 3 3 i i L L[2] L[1] Loca=ons of L are treated Treat L as a single individually monolithic variable 18

DFG Analysis – Loop Unrolling int L[3] = {10, 20, 30}; L[1] = L[1] + L[0]; L[2] = L[2] + L[1]; 19

Transla@ng C to HW • Assump=ons: – Scalar C programs – no pointers and arrays – Implement each statement in a clock cycle. • Basic Idea – Construct CFG and DFG – CFG => controller (control edge -> control sig.) – DFG => datapath (data edges -> comp conn.) • Not very efficient – exist many op=miza=on opportuni=es 20

HW RTL Architecture Control Data Inputs Inputs Control Signals Controller Datapath Status Signals Control Data Outputs Outputs 21

Transla@ng C to HW: Building Datapath • Each variable => a register • MUX is used if a variable is updated in mul=ple statements. • Each expression => a combina=onal logic – Condi=onal expressions => flags to controller • Datapath circuits and registers are connected according to data edges in DFG. 22

Transla@ng C to HW: Building Datapath - - 1: int gcd( int a, int b) { b-a a-b 2: while (a != b) { in_a in_b 3: if (a > b) upd_a 4: a = a - b; upd_b else 5: b = b - a; a b } 6: return a; != } flag_while > out_a flag_if 23

Transla@ng C to HW: Building Controller s1 _ / run1 ! flag_while / _ s2 s6 flag_while / _ _ / run4 s3 Label CFG edges with flags from datapath and ac=ons flag_if / _ ! flag_if / _ that DP should perform, and implement CFG as s4 s5 FSM. _ / run5 24

Transla@ng C to HW: Building Controller flag_while flag_if state in_a in_b Next-state Logic flag_while command flag_if Datapath {_, run1, run4, run5} upd_a upd_b Lookup Table instruction upd_a upd_b _ a b out_a run1 a_in b_in run4 a - b b a b - a run5 upd_a upd_b 25

Limita@ons • Each variable mapped to a register. • A func=onal unit is allocated to every operator. • Performance bojleneck as a single statement is executed in a single clock cycle. – Processor is already doing this. – Can mul=ple statements be executed in a cycle? 26

Transla@ng C to HW: Single-Assignment Form • Each variable is assigned exactly once. • To improve efficiency of the HW implementa=on. a2 = a1 + 1; a = a + 1; a3 = a2 * 3; a = a * 3; a4 = a3 – 2; a = a – 2; 27

Transla@ng C to HW: Single-Assignment Form int gcd( int a1, b1) { int gcd( int a, b) { while (merge(a1, a2) != merge(b1, b2)) { while (a != b) { a3 = merge(a1, a2); if (a > b) a = a – b; b3 = merge(b1, b2); else if (a3 > b3) b = b – a; } a2 = a3 – b3; return a; } else b2 = b3 – a3; } return a; } 28

Transla@ng C to HW: Single-Assignment Form a1 b1 int gcd( int a1, b1) { while (merge(a1, a2) != merge(b1, b2)) { > a3 = merge(a1, a2); a3 b3 b3 = merge(b1, b2); flag_while if (a3 > b3) != a2 = a3 – b3; else flag_while b2 = b3 – a3; } return a; } - - b2 a2 29

Reading Guide • Chapter 4, the CoDesign book. 30