System-on-Chip Design Transac5on-Level Modeling with SystemC Dr. - PowerPoint PPT Presentation

System-on-Chip Design Transac5on-Level Modeling with SystemC Dr. Hao Zheng Comp. Sci & Eng. U of South Florida

Mo5va5on • Why use transac?on-level modeling and ESL languages? - Manage growing system complexity - Enable HW/SW co-design - Speed-up simula?on - Support system-level design and verifica?on • Increase designers’ produc?vity • Reduce development costs and risk • Accelerate ?me-to-market & ?me-to-money 2

Levels of Abstraction Levels of Abstrac5on • Consider models as a function of their time-granularity A. Specification Model “‘Untimed’ Functional Models” A. "Specification model" Communication "Untimed functioal models" B. Component-Assembly Model “Architecture Model” Cycle- B. "Component-assembly model" D F timed "Architecture model" “’Timed’ Functional Model” "Timed functonal model" C. Bus-Arbitration Model C. "Bus-arbitration model" “Transaction Model” "Transaction model" Approximate- C E timed D. "Bus-functional model" D. Bus-Functional Model "Communicatin model" “Communication Model” "Behavior level model" “Behavior-Level Model” E. "Cycle-accurate computation Un- A B model" timed E. Cycle-Accurate Computation Model Computation Un- Cycle- Approximate- F. "Implementation model" timed timed timed F. Implementation Model "Register transfer model" “Register-Transfer Level (RTL) Model” * Figure and taxonomy by Gajski and Cai, UC Irvine 3 Specification Model Objects: Computation: Behaviors Communication: Variables Composition: Hierarchy Execution Order Sequential Parallel Pipelined States Synchronization: Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine

Component-Assembly Model Func5onal Model: Un5med or Timed Computa5on – behavior PE1 Communica5on – abstract Objects: channels B1 cv11 Computation: v1 = a*a; Processors Memories PE3 IP Communications: B3 cv12 A network of v3= v1- b*b; Variable Channels communica?ng Composition: sequen?al processes Hierarchy v3 PE2 connected by abstract Execution Order B4 B2 channels. cv2 v4 = v2 + v3; Sequential v2 = v1 + b*b; c = sequ(v4); Parallel Pipelined States 4 Synchronization: Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine Bus-Arbitration Model Objects: Computation: Processors Memories IP, arbiters Communications: Abstract Bus Channels Composition: Hierarchy Execution Order Sequential Parallel Pipelined States Synchronization: Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine

Bus-Functional Model Bus Func5onal/Arbitra5on Model PE4 (Arbiter) Objects: PE1 Computation: PE3 Processors 3 B1 B3 Memories v1 = a*a; v3= v1- b*b; IP, arbiters Communications: address[15:0] address[15:0] IProtocolSlav 1 data[31:0] 2 data[31:0] ready e ready v3 Protocol Bus Channels ack PE2 ack Composition: B4 B2 v4 = v2 + v3; Hierarchy c = sequ(v4); v2 = v1 + b*b; 1: m ast er i nt er f ace Execution Order 2: sl ave i nt er f ace Sequential 3: ar bi t or i nt er f ace Parallel Pipelined Computa5on – behavioral, approximately 5med States Communica5on – protocol bus channels Synchronization: 5 Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine Cycle-Accurate Computation Model Objects: Computation: Processors Memories IP, arbiters Wrappers Communications: Abstract Bus Channels Composition: Hierarchy Execution Order Sequential Parallel Pipelined States Synchronization: Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine

Bus-Functional Model Objects: Computation: Processors 3 Memories IP, arbiters Communications: 1 2 Protocol Bus Channels Composition: Hierarchy 1: m ast er i nt er f ace Execution Order 2: sl ave i nt er f ace Sequential 3: ar bi t or i nt er f ace Parallel Pipelined States Synchronization: Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine Cycle-Accurate Computation Model Cycle Accurate Computa5on Model PE4 S0 Communica?on is S1 approximately ?med. Objects: S2 S3 Computation: Processors Memories 4 IP, arbiters PE1 PE3 Wrappers 3 MOV r1, 10 MUL r1, r1, r1 4 S0 .... Communications: cv12 S1 Abstract Bus Channels cv2 1 2 4 S2 PE2 cv11 Composition: S3 ... Hierarchy S4 4 MLA r1, r2, r2, r1 .... 1. Master interface Execution Order 2. Slave interface 3. Arbiter interface Sequential 4. Wrapper Communication Parallel Pipelined 6 States Synchronization: Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine

Implementation Model Implementa5on Model PE1 PE2 interrupt interrupt ... MOV r1, 10 MLA r1, r2, r2, r1 MUL r1, r1, r1 .... req req .... Objects: Computation: Processors MCNTR MADDR Memories MDATA IP, arbiters Wrappers PE4 PE3 Communications: S0 Buses/Wires S0 S1 interrupt Composition: S1 S2 Hierarchy S2 S3 Execution Order S3 Sequential S4 Parallel F Pipelined States 7 Synchronization: Notify/Wait * Figure and taxonomy by Gajski and Cai, UC Irvine Characteristics of the Different Models * Figure and taxonomy by Gajski and Cai, UC Irvine

Dataflow Modeling (SystemC-1, Chapter 5) Printer Adder Fork Constant • Actors – processes • communica?ons – FIFO channels - Channels are bounded. • Comm. channel opera?ons – blocking read & write 8

Basic Channel: sc_fifo<T> void void read(T&); read(T&); T read(); read(); bool bool nb_read nb_read(T&); (T&); int int num_available num_available(); (); void write( void write(const const T&); T&); bool bool nb_write nb_write(const const T&); T&); int num_free int num_free(); (); sc_fifo sc_fifo(int int size=16); size=16); sc_fifo sc_fifo(char* name, (char* name, int int size=16); size=16); 9

Ports Compa5ble with sc_fifo<T> sc_fifo_in sc_fifo_in<T> <T>: support only read operations. support only read operations. sc_fifo_out sc_fifo_out<T> <T>: support only write operations. : support only write operations. 10

Dataflow Modeling: Adder template <class T> template <class T> SC_MODULE( SC_MODULE(DF_Adder DF_Adder) { ) { sc_fifo_in sc_fifo_in<T> din1, din2; <T> din1, din2; sc_fifo_out sc_fifo_out<T> <T> dout dout; ; void process() { void process() { while (1) while (1) dout.write dout.write(din1.read() + din2.read()); (din1.read() + din2.read()); } } SC_CTOR( SC_CTOR(DF_Adder DF_Adder) { SC_THREAD(process); } ) { SC_THREAD(process); } }; }; 11

Dataflow Modeling: Constant Generator template <class T> template <class T> SC_MODULE( SC_MODULE(DF_Const DF_Const) { ) { sc_fifo_out sc_fifo_out<T> <T> dout dout; ; void process() { void process() { while (1) while (1) dout.write dout.write(constant_); } (constant_); } SC_HAS_PROCESS( SC_HAS_PROCESS(DF_Const DF_Const); ); DF_Const DF_Const(sc_module_name sc_module_name N, N, const const T& C) T& C) : : sc_module sc_module(N), constant_(C) (N), constant_(C) { SC_THREAD(process); } { SC_THREAD(process); } T constant_; T constant_; }; }; 12

Dataflow Modeling: Fork template <class T> template <class T> SC_MODULE(DF_Fork SC_MODULE( DF_Fork) { ) { sc_fifo_in sc_fifo_in<T> din; <T> din; sc_fifo_out sc_fifo_out<T> dout1, dout2; <T> dout1, dout2; void process() { void process() { while (1) { while (1) { T value = T value = din.read din.read(); (); dout1.write(value); dout1.write(value); dout2.write(value); dout2.write(value); }} }} SC_CTOR( SC_CTOR(DF_Fork DF_Fork) { SC_THREAD(process); } { SC_THREAD(process); } }; }; 13

Dataflow Modeling: Printer template <class T> template <class T> SC_MODULE( SC_MODULE(DF_Printer DF_Printer) { ) { sc_fifo_in sc_fifo_in<T> din; <T> din; void process() { void process() { for ( for (int int i=0; =0; i < < n_iter n_iter; ; i++) { ++) { T value = din.read T value = din.read(); (); cout cout << name() << “ “ <<value<< << name() << “ “ <<value<<endl endl; ; } } done_ = true; return; // terminate done_ = true; return; // terminate } } SC_HAS_PROCESS( SC_HAS_PROCESS(DF_Printer DF_Printer); ); DF_Printer DF_Printer(...) ... { SC_THREAD(process); } (...) ... { SC_THREAD(process); } }; }; 14

Dataflow Modeling: Top Module sc_main sc_main(int int argc argc, char* , char* argv argv[]) { []) { DF_Const DF_Const<int int> constant(“constant”, 1); > constant(“constant”, 1); DF_Adder DF_Adder<int int> adder(“adder”); > adder(“adder”); DF_Fork DF_Fork<int int> fork(“fork”); > fork(“fork”); DF_Printer DF_Printer<int int> printer(“printer”, 10); > printer(“printer”, 10); sc_fifo sc_fifo<int int> > const_out const_out(“ (“const_out const_out”, 5); ”, 5); sc_fifo sc_fifo<int int> > adder_out adder_out(“ (“adder_out adder_out”, 1); ”, 1); sc_fifo sc_fifo<int int> feedback(“feedback”, 1); > feedback(“feedback”, 1); sc_fifo sc_fifo<int int> > to_printer to_printer(“2printer”, 1); (“2printer”, 1); feedback.write feedback.write(42); (42); // channel // channel init. init. ... ... } } 15