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System Design of a Digital High-Speed Modular Satellite Downlink Sren F. Peik Inst. of Aerospace Technology Bremen Outline Motivation Design for Space The DATARAIN System Conclusions Motivation Satellite for Scientific Missions Mass


  1. System Design of a Digital High-Speed Modular Satellite Downlink Sören F. Peik Inst. of Aerospace Technology Bremen

  2. Outline Motivation Design for Space The DATARAIN System Conclusions

  3. Motivation

  4. Satellite for Scientific Missions Mass Instruments Intersatellite Storage Downlink ~1 GBits/s ~1 TBit ~100Mbit/s Link Telemetry Telemetry Link Down Link Ground Ground Station 1 Station 2 User

  5. 1000 MBit/s Ground Station 101101011

  6. Design for Space

  7. Challenge 1: Space Environment Vibration Temperature Vacuum Radiation

  8. Challenge 2: Bandwidth Efficiency CCSDS DSN 8025 8400 f [MHz]

  9. Challenge 3: Reliability

  10. Challenge 4: Doppler Shift C e n t e r f r e q u e n c y o v e r t h e t r a n s m i s s i o n t i m e 8 . 2 0 0 2 8 . 2 0 0 2 8 . 2 0 0 1 v 8 . 2 0 0 1 f [ G H z ] 8 . 2 8 . 1 9 9 9 8 . 1 9 9 9 8 . 1 9 9 8 8 . 1 9 9 8 5 1 0 1 5 2 0 t [ m i n u t e s ]

  11. Requirements: ● CCSDS Compliant ● Space Qualifiable Transmitter ● Low Mass, Low Power System ● X-Band System 8025-8040 MHz, Options for other Bands ● Achievable Rates using α =0.35 Roll-off: Modulation Bit/Hz max. Data Rate QPSK 2 Bit/Hz 555,56 MBit/s 8 PSK 3 Bit/Hz 833,34 MBit/s 16 QAM 4 Bit/Hz 1111,12 MBit/s

  12. The System

  13. DATA OUT DATA IN Transmitter Receiver Channel

  14. Transmitter: 1.4 GHz 8 GHz RF- Baseband IF- Frontend Processor Board Antenna

  15. Blockdiagram Base Band Board IF-Board RF-Front-End X-Band Anti Aliasing Filter I n I I t Image DAC n rejection e t IF-Filter Filter IQ-Mod. Mixer P.-Amp. RF-Filter r e f r FPGA a f c a e c DAC Q e P LO LO LO C RF-Front-End C-Band Image rejection Mixer Filter P.-Amp. RF-Filter 3.3V 5V 12V Power Supply LO

  16. Baseband Processor Base Band Board I n I I t DAC n e t r e f r FPGA a f c a e c Q DAC e P LO C

  17. Baseband Processor Configuration Interface D/A Converter Data Input I+ I- Q+ Q- FPGA Clock Power Supply

  18. Simulation versus Measurement

  19. 16 APSK

  20. IF-Board Anti Aliasing Filter IF Board I IF-Filter IQ-Mod. Q LO

  21. RF Front End RF-Front-End X-Band Image rejection Mixer Filter P.-Amp. RF-Filter LO

  22. RF Spectrum

  23. Receiver Receiver LP-Filter ADC DATA LN-Amp. BP-Filter Mixer BP-Filter AGC Mixer BP-Filter IQ-Demodulator and FPGA LP-Filter Freq. Generator Freq. Generator Freq. Generator

  24. Conclusions ● Space Calls for a Deliberate Design ● High Speed Links are a Challenge for Digital and Analog System Sections ● We still Need Analog Design (Electromagnetic Waves are Analog) ● Interaction of Digital and Analog Sections is a Must

  25. Thank You

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