Stuck-At and Transition N-Detect fault coverage of Pseudo Random - PowerPoint PPT Presentation

EMBEDDEDTESTEMBEDDEDTESTEMBEDDEDTESTEMBEDDED TESTEMBEDDEDTESTEMBEDDED STEMBEDDEDTESTEMBED EMBEDDEDTESTEMBEDDEDTEST STEMBEDDEDTESTEM EMBEDDEDTESTEMBEDDEDTESTEMBEDDEDTESTE EMBEDDEDTESTEMBEDDEDTESTEMBED Stuck-At and Transition N-Detect fault coverage of Pseudo Random and Deterministic Patterns Dwayne Burek BAST 2002 1

At-Speed Test Quality 18 18 Low-speed deterministic Low-speed deterministic 16 16 At-speed deterministic At-speed deterministic At-speed pseudo-random At-speed pseudo-random 14 14 # of Test Escapes # of Test Escapes 12 12 10 10 8 8 6 6 4 4 2 2 0 0 90.00% 90.00% 95.00% 95.00% 98.00% 98.00% 99.00% 99.00% 99.70% 99.70% 100.00% 100.00% Source: ITC ‘95 / Center Source: ITC ‘95 / Center Fault Coverage Fault Coverage for Reliable Computing, for Reliable Computing, Stanford University Stanford University 2  LogicVision, Inc., 2002

Why N-Detect is Important G4 G4 G2 G2 Potential Potential shorts shorts G1 G1 G6 G6 G3 G3 Source: ITC ’00 / Center Source: ITC ’00 / Center for Reliable Computing, for Reliable Computing, Stanford University Stanford University G5 G5 Defects Requiring Multiple Detections 3  LogicVision, Inc., 2002

Logic BIST N-Detect Results 100 100 Percentage of faults detected n times Percentage of faults detected n times 90 90 High-quality test High-quality test 80 80 70 70 60 60 50 50 40 40 30 30 Deterministic: compaction level 4 Deterministic: compaction level 4 20 20 Deterministic: compaction level 1 Deterministic: compaction level 1 Logic BIST Logic BIST 10 10 0 0 5 5 10 10 15 15 20 20 25 25 30 30 Number of detections Number of detections 4  LogicVision, Inc., 2002

Benchmark Circuit � Embedded Logic Test (ELT) Block � Single Clock Domain � Gate Count (extracted): 798192 � Flop Count: 33403 � Test Points: 244 (200 OBS, 44 CNTRL) � DTPG Pattern Count: � Compression Level 1: 4037 � Compression Level 4: 3060 � DTPG Redundant Faults: 0.74 % � DTPG Aborted Faults: 0.22 % 5  LogicVision, Inc., 2002

Logic BIST SA and TR Coverage 100 90 80 NO TP SA NO TP TR 70 TP SA TP TR 60 50 40 15 30 60 120 240 480 960 1920 3840 7680 15360 30720 32768 6  LogicVision, Inc., 2002

Logic BIST N-Detect 100 98 96 TP SA 94 TP TR 92 NO TP SA 90 NO TP TR 88 86 84 1 5 10 15 20 25 30 7  LogicVision, Inc., 2002

Logic BIST vs SCAN ATPG (SA) 100 98 96 94 92 LB SA 90 COMP1 SA 88 COMP4 SA 86 84 82 80 1 5 10 15 20 25 30 No Test Points 8  LogicVision, Inc., 2002

Logic BIST vs SCAN ATPG (TR) 100 95 90 LB TR 85 COMP1 TR 80 COMP4 TR 75 70 65 1 5 10 15 20 25 30 No Test Points 9  LogicVision, Inc., 2002

Logic BIST vs SCAN ATPG (SA) 100 98 96 94 LB SA 92 COMP1 SA 90 COMP4 SA 88 86 84 82 1 5 10 15 20 25 30 244 Test Points 10  LogicVision, Inc., 2002

Logic BIST vs SCAN ATPG (TR) 100 95 90 LB TR 85 COMP1 TR 80 COMP4 TR 75 70 65 1 5 10 15 20 25 30 244 Test Points 11  LogicVision, Inc., 2002

Conclusion � At-Speed pseudo random testing provides superior quality over both low-speed and at- speed deterministic: � Confirmed by Stanford CRC, ITC ’95. � 4 escapes corresponds to DPM level of 720 � Higher levels of Stuck-At and Transition N- Detect coverage result in higher quality test. � Logic BIST Stuck-At and Transition N-Detect coverage can be significantly higher than compacted deterministic ATPG patterns. 12  LogicVision, Inc., 2002