Statistical Device Variability and Statistical Device Variability - PowerPoint PPT Presentation

Statistical Device Variability and Statistical Device Variability and its Impact on Design its Impact on Design Asen Asenov Asen Asenov Device Modelling Group Device Modelling Group University of Glasgow University of Glasgow

Summary Summary Summary � Motivation � Motivation � Deterministic variability � Deterministic variability � Statistical variability � Statistical variability � Impact on circuits � Impact on circuits � EU variability projects � EU variability projects � Conclusions � Conclusions

Summary Summary Summary � Motivation � Motivation � � Deterministic variability � � Deterministic variability Deterministic variability Deterministic variability � � Statistical variability � � Statistical variability Statistical variability Statistical variability � � Impact on � � Impact on circuits Impact on circuits Impact on circuits circuits � � EU variability projects � � EU variability projects EU variability projects EU variability projects � � Conclusions � � Conclusions Conclusions Conclusions

The variability is becoming a major The variability is becoming a major The variability is becoming a major headache headache headache G. Declerck, Keynote talk, VLSI Technol. Symp. 2005

The local stochastic variability becomes The local stochastic variability becomes a major source of concern a major source of concern After D. J. Frank, IBM

Summary Summary Summary � � Motivation � � Motivation Motivation Motivation � Deterministic variability � Deterministic variability � � Statistical variability � � Statistical variability Statistical variability Statistical variability � � Impact on � � Impact on circuits Impact on circuits Impact on circuits circuits � � EU variability projects � � EU variability projects EU variability projects EU variability projects � � Conclusions � � Conclusions Conclusions Conclusions

OPC and strain related variability OPC and strain related variability 65 nm example Synopsys (SISPAD 06) 65 nm example Synopsys (SISPAD 06)

Strain induced variability After W. Fichtner

ECAD tools can deal reasonably well With deterministic variability

Restricted design rules and uniformity Restricted design rules and uniformity After H. Onodera Irregular gate-poly Constant pitch with Constant pitch with � � � dummy poly insertions pitch dummy poly Horizontal poly insertions Stretched gate-poly � � wires Dummy poly extensions � Single orientation patterns � Stretched gate-poly � extensions

Summary Summary Summary � � Motivation � � Motivation Motivation Motivation � � Deterministic variability � � Deterministic variability Deterministic variability Deterministic variability � Statistical variability � Statistical variability � � Impact on � � Impact on circuits Impact on circuits Impact on circuits circuits � � EU variability projects � � EU variability projects EU variability projects EU variability projects � � Conclusions � � Conclusions Conclusions Conclusions

Statistical variability Statistical variability The simulation Paradigm now A 22 nm MOSFET In production 2008 A 4.2 nm MOSFET In production 2023

Random discrete dopants dopants Random discrete Continuous process simulation Atomistic process simulation Synopsys M. Jaraiz KMC Simulator

Line edge roughness (LER) Line edge roughness (LER) Sandia Labs – EUV 1D Fourier synthesis

Poly silicon grain boundaries Poly silicon grain boundaries Poly Si grains, SEM Interdigitised

κ morphology - κ High- morphology High H( x ) α x α κ 1 κ SiO 2 κ 2 κ SiO 2 κ 1 HfSiO HfO 2

Measured and simulated variability Measured and simulated variability LP MOSFETs MOSFETs 45nm technology node 45nm technology node LP 1E-3 1E-5 1E-7 Results from Crolles 2 Results from Atomistic Simulator 1E-9 N-Channel 42 nm gate length 1E-11 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vgs (V) V T V T (50 mV) (1.1 V) Experiment 62 mV 69 mV Simulation 62 mV 67 mV

Combined variability in bulk bulk MOSFETs MOSFETs Combined variability in 13nm 9nm 18nm 25nm 35nm Measured TI IBM Fuj Int LER follows ITRS LER=4nm

The true shape of the distribution The true shape of the distribution Based on the simulation of 100000 transistors Based on the simulation of 100000 transistors

MOSFET capacitance variability MOSFET capacitance variability Gate capacitance Drain capacitance

Interconnect variability Interconnect variability After: T. D. Drysdale LER=5nm 45 nm 32 nm 22 nm delay (p.u.l) LER follows ITRS 45 nm 45 nm 32 nm 32 nm no improvement 22 nm 22 nm 45 nm 32 nm improvement 22 nm delay (p.u.l)

Gate tunnelling leakage variability Gate tunnelling leakage variability Interface pattern Electron distribution Current density

Statistical reliability Statistical reliability Multiple traps Continuous Single trap

Summary Summary Summary � � Motivation � � Motivation Motivation Motivation � � Deterministic variability � � Deterministic variability Deterministic variability Deterministic variability � � Statistical variability � � Statistical variability Statistical variability Statistical variability � Impact on circuits � Impact on circuits � � EU variability projects � � EU variability projects EU variability projects EU variability projects � � Conclusions � � Conclusions Conclusions Conclusions

Deterministic vs. statistic variability Deterministic vs. statistic variability 2 billion transistors: V T1 =200mV V T2 =300mV 3.E+ 08 6.E+ 07 4.E+ 07 5.E+ 07 2.E+ 08 3.E+ 07 4.E+ 07 2.E+ 08 2.E+ 07 3.E+ 07 1.E+ 08 2.E+ 07 1.E+ 07 5.E+ 07 1.E+ 07 0.E+ 00 0.E+ 00 0.E+ 00 0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 1.E+ 08 1.E+ 09 1.E+ 08 1.E+ 08 1.E+ 07 1.E+ 07 1.E+ 07 1.E+ 06 1.E+ 06 1.E+ 06 1.E+ 05 1.E+ 05 1.E+ 05 1.E+ 04 1.E+ 04 1.E+ 04 1.E+ 03 1.E+ 03 1.E+ 03 1.E+ 02 1.E+ 02 1.E+ 02 1.E+ 01 1.E+ 01 1.E+ 01 1.E+ 00 1.E+ 00 1.E+ 00 0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 V G [V] σ V T =10mV σ V T =50mV σ V T =100mV

Compact model strategies 30 L ine s: BSI M3v3 Vgs=0.85V Symbo ls: Data Frequency Vgs=0.75V With parameter rdswmin, 20 nfactor, voff, a1, a2 and d Vgs=0.65V Vgs=0.55V 10 Vgs=0.45V Vgs=0.35V 0 0.8 0.0 0.4 0 5 10 15 20 25 30 Vd (Vo lts) Relative error (%) 30 30 30 30 Frequency Frequency Frequency Frequency with 1-parameter set With parameter vth0, voff With parameter vth0 20 With parameter vth0, voff 20 with 2-parameter set 20 20 with 3-parameter set and rdswmin 10 10 10 10 0 0 0 0 0 5 10 15 20 25 0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30 Relative error (%) Relative error (%) Relative error (%) Relative error (%) BSIM

Impact of bulk MOSFET scaling of SRAM Impact of bulk MOSFET scaling of SRAM 1.0 0.8 V out2 (V) V out 2 [V] 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 V out1 (V) V out 1 [V] 160 160 SNM Mean Value (mV) 30 13nm, SD SNM SD (mV) 18nm, SD <SNM> [mV] σ SNM [mV] 25nm, SD 120 120 20 80 80 13nm, Mean Value 10 18nm, Mean Value 25nm, Mean Value 2 3 4 Cell ratio

Hard logic faults Hard logic faults 1e-4 1e-4 1e-5 1e-5 1e-6 1e-6 V out [V] I D [A] 1e-7 1e-7 1e-8 1e-8 L/W=18/18nm 1e-9 1e-9 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 V in [V] V G [V]

Timing variability Timing variability CMOS NAND 30 CPL NAND DPL NAND Voltage [V] DOMINO NAND Frequency DDCVS NAND 20 10 0 20 30 40 50 60 70 Time [s] Delay (ps)

Performance/Power/Yield (PPY) trade- -off off Performance/Power/Yield (PPY) trade Energy Performance Pareto optimal curve (M. Horowiz, IEDM05) Power Power Yield, % 95 Yield, % 75 95 75 35 35 90nm TG 45nm TG 5 5 Performance Performance

The monitors and knobs approach The monitors and knobs approach The “Technology Aware Design” of IMEC

The Power 6 processor of IBM The Power 6 processor of IBM

Summary Summary Summary � � Motivation � � Motivation Motivation Motivation � � Deterministic variability � � Deterministic variability Deterministic variability Deterministic variability � � Statistical variability � � Statistical variability Statistical variability Statistical variability � � Impact on � � Impact on circuits Impact on circuits Impact on circuits circuits � EU variability projects � EU variability projects � � Conclusions � � Conclusions Conclusions Conclusions

Meeting the Design Challenges of Nano- Meeting the Design Challenges of Nano- CMOS Electronics - eScience Pilot Project CMOS Electronics - eScience Pilot Project University Partners Edinburgh University MMDGUE, NeSCE Glasgow University DMGUG, MSTGUG, NeSCG Manchester University APTGUM, eSNW Southampton University ESDGUS York University ISGUY Industrial Partners Synopsys, ARM, Wolfson Microelectronics, Freescale, National Semiconductors, Fujitsu, NMI Resources £3.3M EPSRC, £4.1M FEC, £5.3M IC 11 PDRAs 7 Science4 e-Sci 7 PhD

Grid based statistical simulation Grid based statistical simulation