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State-of-the-art Multicore Debugging and Tracing concepts by Alexander Merkle, Lauterbach GmbH State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 1 / 20

Agenda AMP or SMP introduction  Debug  Hardware aspects for off-chip debug  Operating system points of view  Trace  Hardware aspects for off-chip trace  Trace timestamping State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 2 / 20

AMP – Asymmetric MultiProcessing Hardware Software A1 Incompatible •Architecture AMP •Instruction Set •Endianness ... B1 State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 3 / 20

AMP – Asymmetric MultiProcessing Hardware Software Set of cores Type A A1 Incompatible •Architecture •Instruction Set •Endianness ... Set of B1 cores Type B State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 4 / 20

SMP – Symmetric MultiProcessing Hardware Software Core Assignment Set of A3 cores A2 Type A A1 Incompatible •Architecture •Instruction Set •Endianness ... B3 Set of B2 cores Type B B1 State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 5 / 20

SMP – Symmetric MultiProcessing Hardware Software Core Assignment Set of A3 cores A2 Type A A1 Incompatible •Architecture •Instruction Set •Endianness ... B3 Set of B2 cores Type B B1 State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 6 / 20

Mixed SMP and AMP configuration Hardware Software Core Assignment SMP-OS Set of A3 cores A2 Type A A1 Incompatible •Architecture AMP •Instruction Set •Endianness SMP-OS ... B3 Set of B2 cores Type B B1 State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 7 / 20

Agenda  AMP or SMP introduction Debug  Hardware aspects for off-chip debug  Operating system points of view  Trace  Hardware aspects for off-chip trace  Trace timestamping State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 8 / 20

AMP or SMP – the offchip debuggers Point of View Debugger Hardware Software Core Assignment Set of A3 cores A2 Type A A1 Incompatible AMP Architecture Endianness ... B3 Set of B2 cores Type B B1 State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 9 / 20

AMP or SMP – the offchip debuggers Point of View MPSoC Chip Architecture Core Debug Debug Level Level Level Toolchain Port Access Access Access Communication Bottleneck (sequential access) State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 10 / 20

SMP – the System Point of View dispatch to one of the SMP-System The SMP-Operating-System (OS) dispatches TASKs to COREs.  As all cores are equal the core to which the task is dispatched is  dynamic. In case of SMP we need to look to the SMP-SYSTEM in total  Debug features must be synchronous to the whole SMP-SYSTEM  → debugging must be synchronous on all cores → onchip hardware assistance for synchronous Go/Break required The external debug tool needs to be aware of the OS and the OS core  assignment. State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 11 / 20

AMP or SMP – the offchip debuggers Point of View MPSoC Core Chip Architecture Core Assignment Debug Debug Level Level Level Toolchain Port Access Access Access Software . . . . Communication Bottleneck (sequential access) State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 12 / 20

SMP or AMP AMP / SMP debug concept AMP SMP Multiple TRACE32 PowerView Single TRACE32 PowerView instances instance State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 13 / 20

Agenda  AMP or SMP introduction  Debug  Hardware aspects for off-chip debug  Operating system points of view Trace  Hardware aspects for off-chip trace  Trace timestamping State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 14 / 20

2. Instruction-Flow == executed code Offchip Trace - Introduction 3. Compress Instruction Flow to Trace-Stream Logical core number 4. Interleaved Stream 1&2 1. execute execute Goal: reconstruct the Instruction-Flow of both cores State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 15 / 20

Trace - Timestamping Challenge:  Trace data is interleaved among all cores of the chip. => Timing information is lost. Recording Signal Processing Ext. Timestamping Δt Transfer HOST State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 16 / 20

Trace - Timestamping Challenge:  Trace data is interleaved among all cores of the chip. => Timing information is lost. Goal:  Reconstruct original „internal“ concurrent trace streams  Correlate the concurrent trace streams  Using either or a mixture of  Assembly level runtime interpolation  Chip global timestamps Accuracy Bandwidth  Cycle accurate traces  Problem:  Bandwidth  State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 17 / 20

Trace - Outlook Parallel to Serial  Low lane count with high bandwidth.  Not only in High-Performance but also in Mid-Range (Realtime) market.  Reuse of standard peripherals like USB, PCI-Express, SATA  Challenges:  trace port is no longer optimized according to it's use-case  System Traces  Instrusive but selective trace of data (software based)  Higher-level evaluation, protocol dependent  State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 18 / 20

Conclusion  Multiprocessor systems use symmetric & asymmetric configurations  Debugging challenges  Target operating system  Chip/core level synchronization (Go/Break)  Debug port bottleneck  Trace challenges  Trace stream correlation/timestamping  Trace port bandwidth State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 19 / 20

Thank you for your Attention Questions? State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 20 / 20