Stage Fractional- N Injection-Locked PLL Using Soft Injection - PowerPoint PPT Presentation

1S-1 An Automatic Place-and-Routed Two- Stage Fractional- N Injection-Locked PLL Using Soft Injection Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan b. b. Matsuzawa Matsuzawa & Okada Lab. & Okada Lab. y y

1S-1 Synthesizable Analog Circuits HDL GDS Digital design flow module PLL (CLK, …, OUT) e.g. Encounter, IC Complier, … Design Compiler, PrimeTime, endmodule Commercial P &R tools… with a standard-cell library without any custom-designed cells without manual placement [W. Deng, et al., ISSCC 2014] 2

1S-1 Integer- N IL-PLL Operation Phase Domain (Integer- N ) ... f PLL D D D D f PLL = N· f ref 4N·2 ɽ P0 Reference e.g. N =3+(1/M) P0 3N·2 ɽ P0 2N·2 ɽ P0 N·2 ɽ t Reference P0 T ref 2·T ref 3·T ref 4·T ref 5·T ref VCO P0  P0  P0  P0  P0  P0 … 3

1S-1 Sub-Integer- N IL-PLL Operation Phase Domain (Sub-Integer- N ) f PLL f PLL = (N+1/M)· f ref P0 P1 P2 ... D D D D P4 4·(N+1/M)·2 ɽ Reference P3 ... 3·(N+1/M)·2 ɽ e.g. N =3+(1/M) 2·(N+1/M)·2 ɽ P2 Reference (N+1/M)·2 ɽ P1 P0 t P0 VCO P1 T ref 2·T ref 3·T ref 4·T ref 5·T ref P2 P0  P1  P2  P3  …  P0  P1 ... … [P. Park, et al., ISSCC 2012] 4

1S-1 Phase Domain (Fractional- N ) f PLL f PLL = (N+0.5/M)· f ref (4·N+2/M)·2 ɽ P2 (3·N+1/M)·2 ɽ P1 (2·N+1/M)·2 ɽ P1 N·2 ɽ P0 t P0 T ref 2·T ref 3·T ref 4·T ref 5·T ref P0  P0  P1  P1  P2  P2  P3 … 5

1S-1 Proposed Soft Injection Injection Reference Signal Soft Injection Reference Soft Injection signal Locked 6

1S-1 Proposed Soft Injection Injection at f 0 Injection at f 8 (D sub =0, D DSM =0) (D sub =7, D DSM =1) Reference f 8 w/o injection “hard” T VCO f 8 w/ injection injection 27 T VCO 28 Soft injection f 8 w/ “soft” injection1 injection f 8 w/ injection2 [W. Deng, et al., ISSCC 2015] 7

1S-1 Design Procedure and Chip Microphoto Verilog Logic RTL 275 m m Logic Synt. Tool Verilog netlist Verilog netlist (gate-level) (gate-level) 175 m m DCO Logic DAC Netlist P&R Tool GDSII Design Procedure CMOS 65nm technology 8

1S-1 Performance Comparison Deng Marucci Elkholy This work ISSCC2014 ISSCC2014 ISSCC2014 CMOS Tech. 65nm 65nm 65nm 65nm 3 0.78 3 10.5 Power [mW] @1.5222GHz @0.9GHz @1.7GHz @0.58GHz Spur [dBc] -53 -47 -51 N/A FoM [dB] -224.2 -236.5 -232 -221.9 Type Frac- N Int- N Frac- N Frac- N Injection DTC-based Injection Topology Soft Injection locking MDLL locking FoM=10log[( j t /1s) 2 (P DC /1mW)] *FOM is calculated based on RMS jitter. 9

1S-1 Conclusion • A synthesizable fractional- N IL-PLL with a soft-injection locking technique is presented. • The proposed fractional-N IL-PLL can achieve fine resolution, low spur with comparable FoM. 10