2-1.1 Spiral 2-1 Datapath Components: Counters Adders Design Example: Crosswalk Controller
2-1.2 Spiral Content Mapping Combinational Sequential System Level Implementation Spiral Theory Project Design Design Design and Tools • • • Performance Decoders and Structural Verilog 1 • metrics (latency muxes Edge-triggered HDL • • • vs. throughput) Synthesis with flip-flops Encoded State CMOS gate • • Boolean Algebra min/maxterms Registers (with machine design implementation • • • Canonical Synthesis with enables) Fabrication Representations Karnaugh Maps process • Synthesis with 2 • • • Bistables, One-hot state MOS Theory muxes & • latches, and Flip- machine design Capacitance, • Shannon's memory • flops Control and delay and sizing • Theorem Adder and • • Counters datapath Memory comparator • Memories decomposition constructs design • • HW/SW Power and other 3 partitioning logic families • • Bus interfacing EDA design • Single-cycle CPU process
2-1.3 Learning Outcomes • I understand the control inputs to counters • I can design logic to control the inputs of counters to create a desired count sequence • I understand how smaller adder blocks can be combined to form larger ones • I can build larger arithmetic circuits from smaller building blocks • I understand the timing and control input differences between asynchronous and synchronous memories
2-1.4 DATAPATH COMPONENTS
2-1.5 Digital System Design • Control (CU) and Datapath Unit (DPU) paradigm – Separate logic into datapath elements that operate on data and control elements that generate control signals for datapath elements – Datapath: Adders, muxes, comparators, counters, registers (shift, with enables, etc.), memories, FIFO’s – Control Unit: State machines/sequencers clk Control reset … … Control Condition Signals Signals Datapath Data Data Inputs Outputs
2-1.6 COUNTERS
2-1.7 Counters • Count (Add 1 to Q) at each clock edge – Up Counter: Q* = Q + 1 – Can also build a down counter as Adder (+) well (Q* = Q – 1) Q Register 1 • Standard counter components include other features – Resets: Reset count to 0 RESET – Enables: Will not count at edge if CLK EN=0 How would you design the – Parallel Load Inputs: Can adder block above for a 4-bit counter? initialize count to a value P (i.e. Only 4-inputs, use T.T. and K- Q* = P rather than Q+1) Maps!
2-1.8 Sample 4-bit Counter • 4-bit Up Counter CE – RST: a synchronous reset P0 Q0 P1 Q1 input 4-bit P2 Q2 CNTR – PE and P i inputs: loads Q P3 Q3 PE with P when PE is active TC RST – CE: Count Enable CLK • Must be active for the counter to count up – TC (Terminal Count) output CLK RST PE CE Q* • Active when Q=1111 AND 0,1 X X X Q counter is enabled • TC = EN•Q3•Q2•Q1•Q0 ↑ 1 X X 0 – Mealy output ↑ 0 1 X P • Indicates that on the next ↑ 0 0 0 Q edge it will roll over to 0000 ↑ 0 0 1 Q+1
2-1.9 Counters CLK RST CE PE P3-P0 1110 1 0000 Q3-Q0 0000 0001 0010 0011 1110 1111 TC SR=active Q*=Q+1 Enable Q*=Q+1 Q*=Q+1 PE = Q*=Q+1 Q*=Q+1 at clock = off, active, edge, thus thus Q thus Q=0 holds Q=P Mealy TC output: EN•Q3•Q2•Q1•Q0
2-1.10 Counter Exercise CLK RST PE CE P[3:0] 0011 1101 1001 Q[3:0]
2-1.11 Counter Design • Sketch the design of the 4-bit counter presented on the previous slides 0 CE 0 + 1 D[3:0] Q[3:0] Q[3:0] P[3:0] 1 Reg PE RST CLR CLK CLK TC
2-1.12 Design a 12-bit Counter CE Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 P0 Q0 P1 Q1 4-bit Q[3:0] P2 Q2 0 0 0 0 0 0 0 0 0 0 CNTR P3 Q3 PE 0 0 0 0 0 0 0 0 0 1 TC RST CLK … 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 CE P0 Q0 P1 Q1 … Q[7:4] 4-bit P2 Q2 CNTR P3 Q3 0 0 0 0 0 1 1 1 1 1 PE TC RST … CLK 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 CE … P0 Q0 Q[11:8] P1 Q1 4-bit P2 Q2 0 0 1 1 1 1 1 1 1 1 CNTR P3 Q3 PE 0 1 0 0 0 0 0 0 0 0 TC RST CLK
2-1.13 Counter Example • Design a circuit that counts each clock cycle to produce the pattern 5, 6, 7, 8, 9, 5, 6, 7, 8, 9, 5...9, 5…9,… CE P0 Q0 P1 Q1 4-bit P2 Q2 CNTR P3 Q3 PE TC RST CLK
2-1.14 ADDERS
2-1.15 Adder Intro • So how would we build a circuit to add two numbers? Adder (+) • Let's try to design a circuit that Q Register 1 can add ANY two 4-bit numbers, X[3:0] and Y[3:0] – How many inputs? RESET – Can we use K-Maps or sum of CLK minterms, etc? 0110 = X + 0111 = Y 1101
2-1.16 Adder Intro • Idea : Build a circuit that performs one column of addition and then use 4 instances of those circuits to perform the overall 4-bit addition • Let's start by designing a circuit that adds 2-bits: X and Y that are in the same column of addition 0110 = X + 0111 = Y 1101
2-1.17 Addition – Half Adders C out • Addition is done in columns 110 – Inputs are the bit of X, Y 0110 = X – Outputs are the Sum Bit and + 0111 = Y Carry-Out (C out ) • Design a Half-Adder (HA) 1101 circuit that takes in X and Y Sum and outputs S and C out 0 1 X Y X Y C out S Half C out 0 0 0 0 0 Adder 0 1 0 1 S 1 0 0 1 1 1 1 1 0
2-1.18 Addition – Half Adders • We’d like to use one 110 adder circuit for each 0110 = X column of addition + 0111 = Y • Problem: 1101 – No place for Carry-out of last adder circuit 0 1 1 1 • Solution – Redesign adder circuit to X Y X Y Half Half include an input for the C out C out 0 1 Adder Adder carry S S 1 0
2-1.19 Addition – Full Adders C out C in • Add a Carry-In input(C in ) 110 • New circuit is called a 0110 = X Full Adder (FA) + 0111 = Y 1101 X Y C in C out S 0 1 0 0 0 0 0 X Y 0 0 1 0 1 0 1 0 0 1 Full 1 C out C in 0 Adder 0 1 1 1 0 S 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1
2-1.20 Addition – Full Adders • Find the minimal 2- level implementations for Cout and S… X Y C in C out S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
2-1.21 Full Adder Logic • S = X xor Y xor Cin – Recall: XOR is defined as true when ODD number of inputs are true…exactly when the sum bit should be 1 • Cout = XY + XCin + YCin – Carry when sum is 2 or more (i.e. when at least 2 inputs are 1) – Circuit is just checking all combinations of 2 inputs
2-1.22 Addition – Full Adders • Use 1 Full Adder for each column of addition 0110 + 0111 X Y X Y X Y X Y Full Full Full Full C out C in C out C in C out C in C out C in Adder Adder Adder Adder S S S S
2-1.23 Addition – Full Adders • Connect bits of top number to X inputs 0110 + 0111 0 1 1 0 X Y X Y X Y X Y Full Full Full Full C out C in C out C in C out C in C out C in Adder Adder Adder Adder S S S S
2-1.24 Addition – Full Adders • Connect bits of bottom number to Y inputs 0110 = X + 0111 = Y 0 0 1 1 1 1 0 1 X Y X Y X Y X Y Full Full Full Full C out C in C out C in C out C in C out C in Adder Adder Adder Adder S S S S
2-1.25 Addition – Full Adders • Be sure to connect first C in to 0 0110 = X + 0111 = Y 0 0 1 1 1 1 0 1 X Y X Y X Y X Y Full Full Full Full C out C in C out C in C out C in C out C in 0 Adder Adder Adder Adder S S S S
2-1.26 Addition – Full Adders • Use 1 Full Adder for each column of addition 01100 0110 = X + 0111 = Y 1101 0 0 1 1 1 1 0 1 X Y X Y X Y X Y 0 1 1 0 Full Full Full Full C out C in C out C in C out C in C out C in 0 Adder Adder Adder Adder S S S S 1 1 0 1
2-1.27 Addition – Full Adders • Use 1 Full Adder for each column of addition 01100 0110 = X + 0111 = Y 1101 0 0 1 1 1 1 0 1 X Y X Y X Y X Y 0 1 1 0 Full Full Full Full C out C in C out C in C out C in C out C in 0 Adder Adder Adder Adder S S S S 1 1 0 1
2-1.28 Addition – Full Adders • Use 1 Full Adder for each column of addition 01100 0110 = X + 0111 = Y 1101 0 0 1 1 1 1 0 1 X Y X Y X Y X Y 0 1 1 0 Full Full Full Full C out C in C out C in C out C in C out C in 0 Adder Adder Adder Adder S S S S 1 1 0 1
2-1.29 Addition – Full Adders • Use 1 Full Adder for each column of addition 01100 0110 = X + 0111 = Y 1101 0 0 1 1 1 1 0 1 X Y X Y X Y X Y 0 1 1 0 Full Full Full Full C out C in C out C in C out C in C out C in 0 Adder Adder Adder Adder S S S S 1 1 0 1
2-1.30 Addition – Full Adders • Use 1 Full Adder for each column of addition 01100 0110 = X + 0111 = Y 1101 0 0 1 1 1 1 0 1 X Y X Y X Y X Y 0 1 1 0 Full Full Full Full C out C in C out C in C out C in C out C in 0 Adder Adder Adder Adder S S S S 1 1 0 1
2-1.31 Performing Subtraction w/ Adders • To subtract 0101 0101 = X – Flip bits of Y + 1100 - 0011 = Y 1 0010 – Add 1 0010 X Y X Y X Y X Y Full Full Full Full C out C in C out C in C out C in C out C in Adder Adder Adder Adder S S S S
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