Specifications & motivation UPPER LIMIT lower much better ! - PowerPoint PPT Presentation

Specifications & motivation UPPER LIMIT lower much better ! • Nr of bits to code a hit : 35 • Fake hit : 10 -5 /event  Lowering integration time would significantly reduce background  Lowering power would significantly reduce material budget Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 2

Status  Low power : Front-end (20.5nA/pixel), shaping(a few μs ) determines integration time  Data driven readout (see Cesar’s presentation)   Two early submissions + Two engineering runs shared with the other groups. Present engineering run delayed to April 9 th . Several chips:   Explorer : sequential analog readout for pixel sensor optimization  Investigator : parallel fast (~10ns rise time) analog readout for pixel sensor optimization  pAlpide : small scale (512x64 array of 22x22 micron pixels) prototypes to optimize circuit  pAlpide_fs : full scale prototype (1024x512 of 28x28 micron pixels) prototype for system studies Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 3

Explorer  Analog readout for pixel characterization  Readout time decoupled from integration time  Possibility to reverse bias the substrate  Sequential readout with correlated double sampling  Contains two 1.8x1.8mm 2 matrices of 20x20 and 30x30 micron pixels with different geometries PULSED ROWS Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 4

Explorer-1 (April 2013) vs Explorer-0 (July 2012) • Comparison of 55 Fe cluster signal for Explorer-0 and Explorer-1 • Explorer-1 shows ~ 2x signal increase, and similar noise level • Confirms correction on input capacitance, circuit contribution reduced from ~4.6 fF to ~2 fF Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 5

Efficiency & fake hit rate (Explorer-0)  High efficiency at low fake hit rates  Reverse substrate bias gives extra margin Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 6

Efficiency & fake hit rate (Explorer-1) Explorer-1 results after tests with electrons at DESY, averaged on all diode geometries • after irradiation drop of 10 - 20% in CCE, recovered with back bias • better performance of larger diodes with larger spacing to electronics • wider distance  wider depletion volume  lower input capacitance • better performance of 20 x 20 µm 2 at low back bias voltage • detection efficiency above 99% up to 10 σ cut, also after irradiation Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 7

pALPIDE pixel circuit diagram Low Power Analog Front End Priority encoder – Reset decoder: Memory cell, hit enabled (< 40 nW/pixel) based on a only zero-suppressed data are during the strobe window. single stage amplifier/current transferred to the periphery. comparator. Front-end output pulse state set Priority encoder reset Pixel State STROBE Register  Circuit capacitance is even smaller than on explorer 1.  First prototype pAlpide-0 works, but two issues:  Source to nwell diode of transistor inside collection electrode competes with resetting diode, “fixed” with light (> 10fA/pixel !!)  Amplifier/comparator stops working for reverse substrate biases > 2 V, due to loss of inversion in NMOS capacitor => could not operate at minimum sensor capacitance  Note: doubling the Pixel State Register significantly reduces dead time (cfr Adam’s simulations) Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March 2014 8

pALPIDE first results Threshold Noise Analog output of one pixel under 55 Fe  Minimum detectable charge <130 e-  At nominal bias (20.5 nA/pixel) and threshold setting:  Threshold spread 17 e-  Noise ~ 7 e-  99.6% efficiency in beam test Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 9

pALPIDEfs Low Power Front-End VPULSE AVDD PMOS Reset Diode Reset C inj 160 aF VRESET VAUX IBIAS ITHR IDB source D0 M0a M0b pix_in M1 Cc VCASN M4 IRESET PIX_OUT_B D1 VCASP M2 AVSS pix_out M5 PWELL curfeed M3 Fixes for two issues: AVSS  Input PMOS transistor outside collection electrode (also for pAlpide1)  Replace for some sectors resetting diode with PMOS transistor Cost: additional capacitance, will have to evaluate impact  Implement capacitor with PMOS instead of NMOS  Also for faster clipping PMOS instead of NMOS clipping transistor Still exploring other alternatives in pAlpides: avoid/minimize the penalty of additional capacitance, further reduce shaping time Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March 2014 10

pALPIDEfs reset scheme PMOS reset Diode reset Collection electrode example Please note that in pALPIDE_fs the nwell is octagonal and the p + ring is squared pwell opening = nwell diameter + 2 . spacing nwell pwell Pulsing capacitor: Sector Columns spacing Reset diameter opening 160 aF 1 0 to 255 2 µm 1 µm 4 µm PMOS 2 256 to 511 2 µm 2 µm 6 µm PMOS Input routing line 3 512 to 767 2 µm 2 µm 6 µm Diode Input PMOS 4 768 to 1023 2 µm 4 µm 10 µm PMOS Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March 2014 11

pALPIDE_fs: 30x15.3mm 1024x512 pixels Pads over the matrix 15.3 mm 30 mm gianluca.aglieri.rinella@cern.ch 12

PADs over matrix: pixel routing 4 metals only  Region of 8x8 pixels allocated for pad over matrix  Provide by-pass for row select and power routing  First results on explorer with metal pads over the matrix promising  Large design effort 8 x 28 µm = 224 µm Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 13

Periphery Matrix DACs Readout I/O pads gianluca.aglieri.rinella@cern.ch 14

Pixels and Priority Encoders Priority Encoder Analog Routing gianluca.aglieri.rinella@cern.ch 15

Readout and I/O pads gianluca.aglieri.rinella@cern.ch 16

Investigator 5.0 mm x 5.8 mm • 135 mini-matrices • Each mini-matrix has 8x8 pixels. • 64 analog outputs to read all the pixels in a mini-matrix. • Different pixel designs: • Pixel width: from 20 x 20 um 2 up to 50 x 50 um 2 • Input transistor inside/outside collection n- well • Continuous diode reset and active PMOS switch reset • Deep-p-well (minimum and maximum) Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March 2014 17

Present engineering run: expected April 9th  CERN/INFN/WUHA N/YONSEI  pALPIDE_fs pALPIDE (3)   EXPLORER (3) INVESTIGATOR   TEST STRUCTURES  RAL CHERWELL3  2 OTHER TEST  CHIPS  IPHC 2 AROM   1 OTHER CHIP Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 18

Conclusions Low power front-end (20.5nA/pixel) with data-driven readout, integration time of a few μs  determined by shaping time of the front end Analog: 20mW/4.5cm 2 , digital not optimized (100mW+200mW)/4.5cm 2 for total chip, serializer  to be added This year one more submission for a further iteration before final decision  Full scale chip : Currently defining features, including interface (see Gianluca’s  presentation)  Several additional building blocks (also on separate test chips):  Bandgap reference & temperature sensor (Nikhef)  Biasing DAC (Yonsei &CERN, already done for first pALPIDE_fs)  Monitoring ADC (INFN, Yonsei, CERN) Serializer (with PLL) & LVDS driver (INFN) (see Gianni’s presentation)   pAlpide(s) : further front-end optimization (reduce C and shaping time)  Investigator & Explorer : further sensor optimization if needed  Front-end & sensor: Benefit of low C clearly established, still measuring different structures and starting materials, issues with front end have forced us to take a penalty for pALPIDE_fs, still exploring further improvements also for reduced shaping time For further details on digital part, see Cesar’s and Alberto’s presentations  Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014 19