Solutions Patrice Joubert Doriol 1 , Aurora Sanna 1 , Akhilesh - PowerPoint PPT Presentation

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions Patrice Joubert Doriol 1 , Aurora Sanna 1 , Akhilesh Chandra 2 , Cristiano Forzan 1 , and Davide Pandini 1 1 STMicroelectronics, Central CAD and Solutions, Agrate Brianza, Italy 2 STMicroelectronics, Central CAD and Solutions, Greater Noida, India IBIS Summit, May 16 th , 2012, Sorrento, ITALY

Today’s I/Os Challenges 2 • Higher I/O account • Increasing operating frequencies • Faster signal edge rates • High I/O density makes it difficult to place PCB decaps close enough to the pads • Automotive specific challenge: I/Os signal conducted EMI • EMC and signal integrity are another mandatory objective for first silicon success IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

EMC At The End Of The Design Flow 3 CMOSM10 Full Mask Set Back-End Metal Fix 6ML $640K $340K 4ML $460K $200K CMOSM55 Expected mask set cost aligned with CMOSM10 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

Our Vision: EMC-Aware Design 4 DESIGN EMC Tools EMC Training Architectural Design EMC Design Guidelines Floorplan Synthesis and Place&Route Verification EMC Simulations EMC Models Compliance? FABRICATION NO EMC compliant YES IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

Reflection, Crosstalk, And SSO Noise 5 Victim + + + + + + + + + + + + + + + + + + + + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Trace 1 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd + + + _ + _ + _ _ + + _ + _ _ _ + _ _ + _ + + _ + _ _ _ + + _ + Chip 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Trace 2 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Chip 1 _ + + _ + + _ + _ _ _ _ + + _ + Trace3 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

SSO Noise And Conducted EMI 6 Switching VDD aggressor Stray capacitance I/O signal VDD Stable noise victim I/O signal conducted Ground emissions V = L·dI/dt inductance Discharge current IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

I/O Ring Circuit 7 • Any realistic signal integrity and EMI simulation must include the complete system-level macromodel (die, package, board) • A full transistor-level simulation of the I/O ring is impractical even for a limited number of adjacent toggling I/Os and a given victim IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

SSO Flow 8 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

SSO Analysis For Automotive Applications 9  STYY : Microcontroller in CMOSM10- 4ML  Size: 4.1x4.1 = 16.81mm 2  Instances: 365K  Main Clock: 64MHz  Package: LQFP144 (Wire bonding) IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

STYY I/O Bank For EMI Analysis 10 Conducted PG15 PAD_111 M Emission BD2S3MS1ARUD_FC_ISO PE14 PAD_78 S Test Pin BD2SS1RUD_FC_ISO PE15 PAD_79 M BD2S3MS1ARUD_FC_ISO PG10 PAD_106 S BD2SS1RUD_FC_ISO PAD_107 Stable Victim PG11 M PG[11] BD2S3MS1ARUD_FC_ISO PC3 PAD_35 S BD2SS1RUD_FC_ISO PC2 PAD_34 M BD2S3MS1ARUD_FC_ISO PA5 PAD_5 M BD2S3MS1ARUD_FC_ISO PA6 PAD_6 S BD2SS1RUD_FC_ISO TMS PAD_TMS M BD2S3MS1ARUD_FC_ISO PC1 PAD_33 F BD3M10FS1ARUDLP_FC_ISO VSS_HV_IO0_N0 Switching aggressors VSSIO_ESDHV_FC_ISO VSS (0V) VSS_HV_FLA0 VSSCO_FC_ISO VDD_HV_FLA0 VDDCO_FC_ISO VDD (5V) VDD_HV_IO0_N0 VDDIO_FC_ISO IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

Design Solutions For SSO Noise Reduction 11 • I/Os’ signal skewing • I/O ring fillercap insertion • I/O pads reduced driving strength • I/O ring power/ground supply placement IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

I/O Skewing Impact on EMI 12 • Typical I/Os’ working frequency for automotive applications are in the range of a few KHz and do not need to toggle synchronously • A relative skew in the range of about 10ns is compatible with a correct functionality of the I/O ring • Harmonic amplitude reduction of several dBµVs obtained in the frequency range of 1GHz On some critical harmonics amplitude reduction of about 10dBµV IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

I/O Fillercaps Insertion And Driving 13 Strength Reduction • I/O fillercap insertion did not prove to be an effective technique • Huge amount of decaps and related area to achieve only few dBµV amplitude reduction • Difficult to exploit this technique on typical pad-limited I/O rings • I/O driving strength reduction (when compliant with the timing constraints) from MEDIUM to SLOW strength version can further reduce the SSO noise IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

SSO Flow Validation 14 • The gate-level SSO flow was validated vs. full Spice-level simulations Aggr. PADs Input Victim PAD Output 1 st Peak (mV) 2 nd Peak (mV) 19.74 39.06 SPICE 20.13 40.93 SSO_AMF IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

IBIS For SSO And EMI Analysis 15 • Traditionally IBIS models have been used for signal integrity simulations on system PCBs • Behavioral modeling • IP protection • Fast simulation time • Reasonable accuracy • However IBIS v4.0 cannot include predriver and crossbar currents and I/O ring power/ground supply bouncing which is the dominant source of SSO and conducted EMI • To validate IBIS v5.0 for EMI analysis the same STYY I/O bank was used • IBIS v5.0 was compared vs. full transistor-level simulations IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

IBIS Validation Flow 16 I/Os I/Os Spice netlist IBIS model Board model power and Package model SPICE signal traces Time- domain waveforms SSO Spectra Frequency-domain analysis Conducted EMI IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

IBIS For SSO And EMI Analysis 17 IBIS v5.0 vs. Spice Time-domain analysis Frequency-domain analysis IBIS vs. Spice: good accuracy up to 2GHz IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012

Summary 18 • CAD flow and design solutions for SSO and I/O conducted EMI analysis and optimization were presented • Methodology exploited on an industrial automotive microcontroller in ST 90nm with eNVM technology • IBIS v5.0 can be used for a reliable SSO and EMI analysis IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions 08/05/2012