conference & convention enabling the next generation of networks & services Soft Decision Based Triple-Concatenated FEC for 100 Gb/s Submarine Cable Systems K. Onohara, K. Kubo, Y. Miyata, H. Yoshida, and T. Mizuochi Mitsubishi Electric Corporation
conference & convention enabling the next generation of networks & services Presenter Profile Kiyoshi Onohara received the B.E., M.E., and Ph.D. degrees in communication engineering from Osaka University, Osaka, Japan, in 2000, 2002, and 2005, respectively. In 2005, he joined Mitsubishi Electric Corporation, In 2005, he joined Mitsubishi Electric Corporation, Kamakura, Kanagawa, Japan, where he has been engaged in research and development of the applications of forward error correction, optical cross-connect, and supervisory system for optical transport networks. Kiyoshi Onohara Researcher Email: Onohara.Kiyoshi@eb.MitsubishiElectric.co.jp Tel: (+81) 467 41 2443 2
conference & convention enabling the next generation of networks & services Outline Introduction � Motivation for Developing Strong FEC for 100 Gb/s Systems Soft Decision FEC in Digital Coherent Transceivers Triple-Concatenated FEC Triple-Concatenated FEC � Algorithm of the proposed FEC � Simulation result Impact on the Next Gen. Submarine Cable Systems Conclusion 3
conference & convention enabling the next generation of networks & services Needs Higher SNR for 100Gb/s Systems � In the pursuit of high speed transmission, we should consider that multi-level modulation needs a higher SNR than binary formats. � This has increasingly motivated research activity of more powerful, but nevertheless practical FEC for the improvement of OSNR tolerance in 100G digital coherent systems. PSK 18 m) Required OSNR (dB in 0.1nm) 16 DP-16QAM QPSK 14 OOK DP-16QAM DP-QPSK 12 DQPSK 8-PSK 1.3dB DPSK 10 2.7dB DP-QPSK 8 DQPSK OOK 16-QAM 6 5.7dB 4 DPSK 64-QAM 2 10 20 40 100 4 Bit rate (Gb/s)
conference & convention enabling the next generation of networks & services Soft Decision FEC in Digital Coherent (1) � Conveniently, a digital coherent receiver incorporates A/D converters (ADCs) at its front-end for demodulating multi-level coded signals � This suddenly makes it much easier to realize soft-decision decoding 6-bit 6-bit 3-bit Digital Coherent LSI 100G 6-bit ADC DP-QPSK DP-QPSK DP-QPSK DP-QPSK Euclidean Euclidean Soft Dec. DSP 6-bit ADC Corrected Distance RX FEC (CR, FDE Output 6-bit ADC Decoder Pol. Demux) Module LLR Calc. 6-bit ADC (01) (00) r Euclidean Distance (11) (10) 5 DSP: Digital Signal Processor, CR: Carrier Recovery, FDE: Frequency Domain Equalizer, LLR: Log-likelihood Ratio
conference & convention enabling the next generation of networks & services Soft Decision FEC in Digital Coherent (2) � OIF proposed that the low-redundancy hard decision FEC on OTU4 framer as the outer codes. � The inner FEC encoder/decoder is implemented into transceiver module as an option. � The concatenation with 7% EFEC and soft decision FEC is good solution. � This architecture facilitates the implementation issues underlying not only transceiver module but also 100G framer. Digital Signal Processor Digital Signal Processor OTU4 Framer and EFEC with Soft-decision LDPC Soft-decision LDPC Hard-decision EFEC (inner code) (outer code) I/O I/O Code C Code A Code B OTU4 DSP ENC ENC ENC Client E/O Channel Framing / MUX Optical I/O I/O Digital OTU4 Coherent DEC DEC Client DEC De- O/E RX framing /DEMUX Iteration 6
conference & convention enabling the next generation of networks & services Triple-Concatenated FEC � LDPC is one of the potential candidates for strong soft decision FEC in 100Gb/s systems. � The redundancy of the LDPC(9216,7936) developed in 2009, is 16%. � The ratio of the LDPC(4608,4080) code of the proposed triple-concatenated FEC with Enhanced FEC is 13%. � By applying the shorter code length of LDPC, we suffer from the error floor performance. Therefore LDPC concentrates the water fall region, and we use Enhanced FEC as the outer code. This does not degrade, but assists the coding gain. LDPC: Low-Density Parity Check Conventional FEC and frame format 4% 16% Post-FEC BER row1 row2 RS OH Payload LDPC ~10 -5 row3 row4 Pre-FEC BER Proposed FEC and frame format Post-FEC BER 7% 13% ~10 -3 row1 EFEC row2 OH Payload LDPC row3 Pre-FEC BER row4 Inner FEC Outer FEC OTU4 frame 7 decoding decoding
conference & convention enabling the next generation of networks & services Algorithms for LDPC � Conventional algorithms for LDPC codes � Shuffled belief propagation (BP) algorithm – High-performance, but quite complex � Offset BP-based algorithm variable offset BP variable offset BP – Approximation of shuffled BP – Performance is not so good cyclic approx. d-min cyclic approx. d-min ood ood Goo Goo easy easy shuffled BP shuffled BP calculation calculation Performance Performance � We propose new algorithm; Variable offset BP-based algorithm offset BP offset BP – Designed to minimize the circuit upgrade upgrade complexity without degrading error NCG NCG correction performance. Bad Bad – This algorithm originated from the min-sum min-sum offset BP-based algorithm. Small Small Complexity Complexity Large Large Comparison of decoding algorithms NCG : Net Coding Gain 8
conference & convention enabling the next generation of networks & services Comparison of Algorithms • Error Correction Performance – Performance evaluation by Monte Carlo simulations – Variable offset BP-based algorithm is better than the offset BP-based algorithm, the difference being about 0.1 dB. Uncoded Uncoded 1E+00 1E+00 Variable offset BP-based Variable offset BP-based Offset BP-based Offset BP-based 1E-01 1E-01 Cyclic approx. delta min Cyclic approx. delta min Shuffled BP Shuffled BP Shuffled BP Shuffled BP 1E-02 1E-02 Bit Error Ratio Bit Error Ratio Simulation conditions 1E-03 1E-03 Parameters of inner LDPC 1E-04 1E-04 code (4608, 4080) 1E-05 1E-05 Redundancy 12.94% 1E-06 1E-06 Bit width of LLR 3 (Input of decoder) 1E-07 1E-07 Noise model AWGN 1E-08 1E-08 5.5 5.5 6.0 6.0 6.5 6.5 7.0 7.0 7.5 7.5 Q [dB] Q [dB] Simulation results LLR : Log-Likelihood Ratio 9
conference & convention enabling the next generation of networks & services Performance Evaluation • Performance evaluation by Monte Carlo simulations – LDPC+EFEC has no error floor at least down to a post-FEC BER of 1E-11 – We expect that proposed concatenated codes can achieve a Q-limit of 6.4 dB (NCG of 10.8dB) at a post-FEC BER of 1E-15. • 4.6 dB better than the standard RS(255,239) code 1E-01 1E-01 1E-01 1E-03 1E-03 1E-03 Bit Error Ratio Bit Error Ratio Bit Error Ratio 1E-05 1E-05 1E-05 1E-07 1E-07 1E-07 1E-09 1E-09 1E-09 Uncoded Uncoded Uncoded LDPC only LDPC only LDPC only 1E-11 1E-11 1E-11 LDPC + EFEC LDPC + EFEC LDPC + EFEC 1E-13 1E-13 1E-13 1E-15 1E-15 1E-15 5.5 5.5 5.5 6.0 6.0 6.0 6.5 6.5 6.5 7.0 7.0 7.0 7.5 7.5 7.5 10 Q [dB] Q [dB] Q [dB]
conference & convention enabling the next generation of networks & services Impact on Next Gen. Submarine Cable Systems � A digital coherent transceiver with this powerful FEC pushes a submarine line terminal equipment (SLTE) with 100 Gb/s interfaces towards fruition. � A range of interfaces: 2 x 40 Gb/s and 10 x 10 Gb/s � Relief from the need for dispersion compensation fibers by implementing a dispersion compensator in the DSP dispersion compensator in the DSP � Pure-silica fiber can be installed when constructing new cable systems, resulting in reduced capital expenditure � The powerful FEC enables us to migrate from existing 40 Gb/s long-haul systems to 100 Gb/s DP-QPSK systems 100G DP-QPSK 40G DPSK with SD-FEC with EFEC Upgrade Scenario for submarine cable systems 11
conference & convention enabling the next generation of networks & services Conclusion � We have proposed the triple-concatenated FEC for 100 Gb/s submarine cable system. � New algorithms of LDPC codes for soft-decision FEC were proposed. � We showed the performance of LDPC(4608, 4080)+EFEC by Monte Carlo � We showed the performance of LDPC(4608, 4080)+EFEC by Monte Carlo simulation. Expected to achieve a Q-limit of 6.4dB (NCG of 10.8dB) at a post- FEC BER of 1E-15. � It is anticipated that the proposed FEC scheme will be implemented in 100 Gb/s coherent DSP LSI in the near future. This work was in part supported by the project of “Digital Coherent Optical Transceiver Technologies” of the Ministry of Internal Affairs and Communications (MIC) of Japan 12
2010 conference & convention enabling the next generation of networks & services The 7th International Conference & Convention on Undersea Telecommunications Pacifico Convention Plaza Yokohama & InterContinental The Grand Yokohama 11 ~ 14 May 2010 www.suboptic.org
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