Shallow Junctions & Contacts Prof. Krishna Saraswat - PDF document

Shallow Junctions & Contacts Prof. Krishna Saraswat Department of Electrical Engineering Stanford University Stanford, CA 94305 saraswat@stanford.edu Stanford University 1 Saraswat / EE311 / Shallow Junctions Outline • Junction/contact scaling issues • Shallow junction technology • Ohmic contacts • Technology to form contacts Stanford University 2 Saraswat / EE311 / Shallow Junctions Page ‹#›

MOS Device Scaling L Constant E Field Scaling x X j All device parameters are scaled by ox L the same factor. N+ x ox X j N+ N a N+ N a N+ • gate oxide thickness x ox ↓ l l o o P • channel length L ↓ P • source/drain junction depth X j ↓ • Channel doping ↑ Why do we scale MOS transistors? • Supply voltage V DD ↓ 1. Increase device packing density 2. Improve frequency response α 1/L 3. Improve current drive (transconductance g m ) g m = � I D � V V D = const G � W K o x V D for V D < V D SAT , linear region L µ n t o x � W K o x L µ n ( V G � V T ) for V D > V D SAT , saturation region t o x Why do we need to scale junction depth? Stanford University 3 Saraswat / EE311 / Shallow Junctions Short Channel Effects on Threshold voltage Ddepletion width in a long channel device 2 � (2 � F + V BG ) W = Gate qN A We can approximate, the bulk charge as L Depletion N+ source N+ drain Q B � L = q � N A � W � L + L ' � � region � � rj L � � � 2 � � P-Si By trigonometry, we can write: Q depleted Q depleted B B by source by drain � � L + L ' r j 1 + 2 � W � � = 1 � � 1 � � � 2 L r j L � � We can then approximate the threshold voltage as: � � � � r j V T = V FB � 2 � � F � Q B 1 + 2 � W � 1 � � � 1 � � � � C ox r j L � � � � Threshold voltage is a function of junction depth, depletion width and channel length? L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974 Stanford University 4 Saraswat / EE311 / Shallow Junctions Page ‹#›

Need for Shallow Source/Drain Junctions � � � � r j V T = V FB � 2 � � F � Q B 1 + 2 � W � 1 � � 1 � � � � � C ox r j L � � � � •Roll-off in threshold voltage as the channel length is reduced and drain voltage is increased •To minimimize V T roll-off •Reduce as junction depth(r j ) •Increase in C ox should increase gate control Sheet resistance increases as junction depth is reduced Stanford University 5 Saraswat / EE311 / Shallow Junctions Source/drain Junction Depth Year 1997 1999 2003 2006 2009 2012 Min Feature Size 0.25 � 0.18 � 0.13 � 0.10 � 0.07 � 0.05 � Contact x j (nm) 100-200 70-140 50-100 40-80 15-30 10-20 x j at Channel (nm) 50-100 36-72 26-52 20-40 15-30 10-20 From the ITRS roadmap •Source/drain doping requirements show continuing drive to obtain shallow junctions. •How will we form such shallow junctions? •How will we make low resistance contacts to them? •How will we minimize the sheet resistance of the junctions? Stanford University 6 Saraswat / EE311 / Shallow Junctions Page ‹#›

S/D Junction Scaling Trend Gate Length or SDE Depth [nm] 70 60 2001 ITRS 60 Physical Gate Length 50 ] 50 % Max. Ratio of R sd to Ideal R ch 40 [ 40 l a e 30 d i - 30 h c R 20 / 20 d L t s ⇒ Scaled with L g R R ch ox � 10 ch ( V V ) 10 (L ch ↓ , t ox ↓ ) � gs th SDE Junction Depth 0 0 2000 2004 2008 2012 2016 1 Year ⇒ Difficult to scale R R � � sd sh N X (N sd const, X j ↓ ) sd j Ref: J. Woo (UCLA) ⇒ R sd /R ch ↑ • As L g scales down, R sd becomes comparable to R ch • R sd becomes important factor for device current • Parasitic portion of the device is now playing important role in device performance and CMOS scaling Stanford University 7 Saraswat / EE311 / Shallow Junctions Impact of Parasitic Series Resistance Series Resistance (ohms) y = 0 140 NMOS 120 Scaled by ITRS Roadmap R 100 ov Sidewall Gate 80 R 60 ext Silicide R x 40 N ov ( y ) dp R ov R R csd 20 R ext R dp csd 0 30 nm 50 nm 70 nm 100 nm Physical Gate Length N ext ( x ) 70 Relative Contribution [%] 60 R csd Problem in junction scaling: NMOS • Sheet resistance of a junction is a strong 50 function of doping density 40 R ext • Maximum doping density is limited by solid 30 solubility and it does not scale ! R ov • Silicidation can minimize the impact of 20 junction sheet resistance 10 R dp • Contact resistance R csd is one of the dominant 0 components for future technology 32 nm 53 nm 70 nm 100 nm Physical Gate Length Source: Jason Woo, UCLA Stanford University 8 Saraswat / EE311 / Shallow Junctions Page ‹#›

Relative Contributions of Resistance Components: PMOSFETs 70 Relative Contribution [%] Series Resistance (ohms) R csd PMOS 200 PMOS 60 Scaled by ITRS Roadmap R 50 150 ov 40 100 R ov R 30 ext R 20 50 R ext R dp dp R 10 csd 0 30 nm 50 nm 70 nm 100 nm 0 32 nm 53 nm 70 nm 100 nm Physical Gate Length Physical Gate Length Problem even more serious for PMOS • R csd will be a dominant component for highly scaled nanometer • transistor ( R csd /R series ↑ >> ~ 60 % for L G < 53 nm) Source: Jason Woo, UCLA Stanford University 9 Saraswat / EE311 / Shallow Junctions Outline • Junction/contact scaling issues • Shallow junction technology • Ohmic contacts • Technology to form contacts Stanford University 10 Saraswat / EE311 / Shallow Junctions Page ‹#›

Dopant Diffusion Ion Implant Gate Stack Anneal/Diffusion • Solutions to diffusion equations (Fick's laws) gives bulk diffusivity _ E O k � T o � e D i = D i • In shallow junction technologies, numerous effects alter these values resulting in enhanced diffusion. • Transient enhanced diffusion _ t � D = D i + D o � e • Diffusion affected by defects, e.g.,oxidation induced point defects Stanford University 11 Saraswat / EE311 / Shallow Junctions Diffusion Affected by Oxidation Induced Point Defects TSUPREM IV simulations of oxidation enhanced diffusion of boron (OED) and oxidation retarded diffusion of antimony (ORD) during the growth of a thermal oxide on the surface of silicon. antimony boron Oxidation increases interstitials (C I ) and decreases vacancies (C V ) from their equilibrium values. This in turn changes diffusivity. (Ref: Plummer, et al., Silicon VLSI Technology - Fundamentals, Practice and Models) Stanford University 12 Saraswat / EE311 / Shallow Junctions Page ‹#›

Diffusion in Polycrystalline Materials D GB grain boundary diffusion D L lattice diffusion Generally D GB >> D L The worst-case demonstration of the defect enhanced diffusion of dopants is in polycrystalline silicon, which can be several times faster than diffusion in bulk Si because of defects at the grain boundaries. Stanford University 13 Saraswat / EE311 / Shallow Junctions Transient Enhanced Diffusion (TED) 40 keV, 10 -14 cm -2 B 750ºC anneal τ At lower temperatures, the damage can stay around longer and enhance the dopant diffusion, while at higher temperatures the damage annihilates faster. Thus the diffusivity is a function of time during the transient. D = D i + D o � exp � t � � o exp � E 0 � � is intrinsic diffusity � � Where D i = D i � � � � � � kT � Ref: Plummer, et.al., Stanford University 14 Saraswat / EE311 / Shallow Junctions Page ‹#›

Effect of TED on Junction Depth • At lower temperature longer times are needed to anneal the damage • Transient enhanced dopant diffusion effects are stronger • Junction depth is larger • Higher temperature and shorter times are needed to minimize TED Stanford University 15 Saraswat / EE311 / Shallow Junctions Shallow Junction Formation Technologies Low Energy Implantation 40 keV As and B implants 12 keV B implants Concentration (cm -3 ) Concentration (cm -3 ) Boron Boron BF 2 Arsenic Depth Depth As Concentration (cm -3 ) 10 22 as-implanted 10 20 5 keV 1 keV Ref. Kasnavi, PhD Thesis 10 18 Stanford Univ. 2001 10 16 0 20 40 60 80 Depth (nm) Stanford University 16 Saraswat / EE311 / Shallow Junctions Page ‹#›

Ion Implantation Damage Heavy ions (As, P) Light ions (B) Higher energy Lower energy • Heavy ions (As, P) cause excessive damage turning implanted region into amorphous • Light ions (B) have buried damage Stanford University 17 Saraswat / EE311 / Shallow Junctions Ion Implantation Damage Anneal Light ions (B) Heavy ions (As, P) Lower energy Higher energy Amorphous After implant regrowth Crystalline SPE After anneal fully annealed Buried damage • Fully amorphized region can be fully annealed through solid phase regrowth • Buried damage leaves defects where damage was created as regrowth takes place both from top and bottom. Stanford University 18 Saraswat / EE311 / Shallow Junctions Page ‹#›

Pre-amorphization implants Log concentration (cm -3 ) Implanted 10 sec 1000°C RTA Ge preamorphized Si preamorphized Not preamorphized Depth (nm) Pre-amorphization implants can reduce the damage and yet get shallow junctions Stanford University 19 Saraswat / EE311 / Shallow Junctions Solid Source Diffusion ) -3 m c ( n o i t a r t n e c n o C B Depth (nm) Depth (nm) In COSi 2 In Si after silicide removal Boron profiles after diffusion at 950°C of 50 nm COSi 2 implanted with 5 X 10 15 cm -2 BF 2 (a) and (b)in Si after silicide removal. Stanford University 20 Saraswat / EE311 / Shallow Junctions Page ‹#›