ROAD: Routablility Analysis & Diagnosis Based on SAT Techniques - PowerPoint PPT Presentation

ROAD: Routablility Analysis & Diagnosis Based on SAT Techniques ISPD 2019 UCSD VLSI LAB Dongwon Park , Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng 1

P HYSICAL D ESIGN GETTING H ARDER P HYSICAL D ESIGN GETTING H ARDER • Design Rule Complexity Rising • Keep Scaling Technologies • Tons of design rules from multi-patterning technology • Limited Resource (# of Routing Track) Detailed Routing is getting complex and bottleneck. 2/47

I. Routability Analysis 3

D ESIGN R ULE -C ORRECT R OUTABILITY A NALYSIS ILP: Optimal but 1048s (~18min) ! Gate Netlist Placement Given Pin-Layout SAT : Not Optimized but 2s !!!!! Power Rail Pin 16 15 14 11 4 6 2 8 9 17 19 21 23 22 20 Routable? 18 Pin 12 13 0 1 5 3 7 10 SAT Method → Quick “go/no - go” Decision Via3-4 M1-2 M2-3 M3-4 4/47

R OUTABILITY A NALYSIS F RAMEWORK • ILP-based routability optimization • SAT-based routability analysis Fast and Precise Routability Analysis w Our Proposed Framework Routability Analysis Flow Inputs Testcase (i.e., Switchbox) Generation - #Vertical and Horizontal Tracks Logic Simplification - Pin Density ILP Patterns Switchboxes SAT-Friendly ILP Formulation per ILP Formula - 3D Routing Graph - Source-Sink Definition Logic Minimizer ILP-to-SAT Conversion ILP Inputfiles Espresso [26] ILP Solver SAT Reduced SAT SAT Solver Portfolio Solvers Inputfiles Inputfiles CPLEX [27] Plingling / Glucose-syrup / many-Glucose ILP Result: Routing Feasibility, Results of Wirelength, Metal Cost, etc. by SAT by ILP SAT Result: Routing Feasibility, Routability Analysis SAT Solution if Satisfiable [27] IBM ILOG CPLEX, http://www.ilog.com/products/cplex/. 5/47 [28] plingeling, Multi-Threading SAT Solver, http://fmv.jku.at/lingeling/.

P ROPOSED ILP/SAT F ORMULATION D IAGRAM ▪ The Multi-commodity network flow formulation (F) ▪ Conditional Design Rule (D) ▪ Layout Structure Map (L) Flow Formulation (F) Design-Rules Formulation (D) 𝑤 Exclusiveness 1. End-of-Line Space Rule (EOL) Commodity Flow Use Conservation 2. Minimum Area Rule (MAR) of Vertex (EUV) (CFC) 3. Via Rule (VR) 𝑜 (𝑤, 𝑣) 𝑜 𝑔 𝑓 𝑤,𝑣 𝑛 Edge Assignment (EA) Metal Segment (MS) Geometry Variable (GV) 𝑛 𝑤,𝑣 𝑕 𝑒,𝑤 Layout Structure Map (L) 6/47

SAT F ORMULATION – F LOW F ORMULATION (F) ▪ Commodity Flow Conservation (CFC) ▪ CASE I) Vertex ≠ source, sink : 0 or 2 edges uses 1) Only one incoming/outgoing pair is allowable for all 2) This commodity don’t use this vertex. commodities. (𝑤) (𝑤) (𝑤) (𝑤) (𝑤) 𝑜 (𝑤, ) 𝑜 (𝑤, ) 𝑔 𝑔 𝑛 𝑛 𝑜 (𝑤) 𝑔 (𝑤) 𝑜 (𝑤) 𝑔 𝑛 𝑛 (𝑤) (𝑤) (𝑤) (𝑤) ▪ CASE II) Vertex = source, sink : Exactly-One (EO) Commodity Flow Constraint. (𝑤) (𝑤) 𝑜 (𝑤, ) 𝑔 𝑛 𝑜 (𝑤) 𝑔 (𝑤) 𝑛 (𝑤) (𝑤) 7/47

SAT F ORMULATION – F LOW F ORMULATION (F) ▪ Exclusiveness Use of Vertex (EUV) ▪ CASE I. Vertex ≠ source, sink : At-Most-One (AMO) Net Constraint 2) No Flow 1) Only one net can use a certain edge (𝑤) 𝑣 𝑜 𝑓 𝑤,𝑣 (𝑤) (𝑤) (𝑤) 𝑜 𝑜 𝑓 𝑤, 𝑓 𝑤,𝑣 (𝑤) 𝑣 (𝑤) (𝑤) (𝑤) (𝑤) ▪ CASE II. Vertex = source, sink : Exactly-One (EO) Edge Constraint (𝑤) (𝑤) 𝑜 𝑓 𝑤, (𝑤) (𝑤) (𝑤) 8/47

SAT F ORMULATION – F LOW F ORMULATION (F) ▪ Edge Assignment (EA) 𝑜 (𝑤, 𝑣) → 𝑓 𝑤,𝑣 𝑜 𝑔 𝑛 Logical Imply. : edge is used by n net if m commodity of n net use this edge → It requires for multi-commodity flow ▪ Metal Segment (and Exclusiveness Use of Edge) (MS) ▪ Commander Encoding Variable of EO constraint of edge indicators 9/47

SAT F ORMULATION – D ESIGN R ULE F ORMULATION (D) ▪ Geometric Variable (GV) ▪ End-of-Line indicator of each vertex for geometric conditional design rule. (𝑤, 3) 𝑕 𝐶,(𝑤,2) = 1 (𝑤, 2) 𝑕 𝑆,(2,𝑤) = 1 𝑕 𝑀,(1,𝑤) = 1 (𝑤, 1) 𝑕 𝐺,(𝑤,1) = 1 (0, 𝑤) (1, 𝑤) (2, 𝑤) 10/47

SAT F ORMULATION – D ESIGN R ULE F ORMULATION (D) ▪ Minimum Area Rule (MAR) ▪ A metal segment must cover at least three vertices (AMO Constraint) No Violation Violation 𝑤 𝑀 𝑤 𝑤 𝑤 𝑀 𝑕 𝑆,𝑤 = 𝑕 𝑀,𝑤 𝑀 = 1 𝑕 𝑆,𝑤 = 1 𝑕 𝑀,𝑤 = 𝑕 𝑀,𝑤 𝑀 = 𝑕 𝑆,𝑤 𝑀 = 0 𝑕 𝑀,𝑤 = 𝑕 𝑆,𝑤 𝑆 = 0 11/47

SAT F ORMULATION – D ESIGN R ULE F ORMULATION (D) ▪ End-of-Line (EOL) Space Rule ▪ The minimum distance between tips must be larger than 2 Manhattan distance (AMO Constraint) 𝑤 𝐶𝑆 𝑤 𝐶𝑆 𝑤 𝐶𝑆 𝑤 𝑤 𝑆 𝑤 𝑆𝑆 𝑤 𝑤 𝑆 𝑤 𝑆𝑆 𝑤 𝑤 𝑆 𝑤 𝑆𝑆 𝑤 𝐺𝑆 𝑤 𝐺𝑆 𝑤 𝐺𝑆 Violation Violation No Violation 12/47

SAT F ORMULATION – D ESIGN R ULE F ORMULATION (D) ▪ Via Rule (VR) ▪ The distance between two vias should be larger sqrt(2) Euclidean Distance (AMO constraint) 𝑁 𝑗+2 𝑁 𝑗+2 𝑁 𝑗+1 𝑁 𝑗+1 𝑤 𝑉𝐶 𝑤 𝑉𝐶𝑀 𝑤 𝑉𝐶𝑆 𝑤 𝑉 𝑤 𝑉𝑀 𝑤 𝑉𝑆 𝑤 𝐶𝐶 𝑤 𝑉𝐺𝑆 𝑤 𝑉𝐺 𝑁 𝑗 𝑤 𝑉𝐺𝑀 𝑁 𝑗 𝑤 𝐶𝑀 𝑤 𝐶 𝑤 𝐶𝑆 𝑤 𝑤 𝑀 𝑤 𝑤 𝑆 𝑤 𝐺𝑀 𝑤 𝐺 𝑤 𝐺𝑆 𝑤 𝐺𝐺 No Violation Violation 13/47

D ESIGN R ULE -C ORRECT R OUTABILITY A NALYSIS ▪ Flow Feasibility (F) ▪ Conjunction of each subsets ▪ Design Rule Formulation (D) ▪ Design Rule-correct Routability ( R ) ▪ L : Layout Structure Map → the geometry information of the switch box 14/47

15 II. Routability Diagnosis 15/47

N EXT S TEP : R OUTABILITY D IAGNOSIS ▪ Conflict Diagnosis in Unroutable Case using SAT Technique ▪ Exact Location of Conflict → Fast Trouble-shooting for Designer ▪ Exact Conflict Relation → Guideline for Design Rule Manager 16/47

ROAD : O VERVIEW OF D IAGNOSIS Routability Analysis Using SAT Formulation Unroutable Layout Node : U (variable) MUS MUS Extraction (Minimal Unsatisfiable Subset) Clause Minimization U b Edge : D (clause) Initial Propagation (Geometric Information of Switch-Box) Conflict Region PIG BCP U s Decision (DLS) Iteration (Decision with Longest-Path Search) U p Propagation (PTA/PFA) (Propagation with True/False Assignment) No Conflict? Yes DAG : H(U,D) Conflict Information (Conflict Geometry / Design Rule) 17/47

(1) M INIMAL U NSATISFIABLE S UBSET (MUS) 18/47

(2) BCP (B OOLEAN C ONSTRAINT P ROPAGATION ) & PIG ▪ PIG (Partial Implication Graph) in Our Framework ▪ Directed Acyclic Graph which Nodes are Variables, Edges are Clauses. ▪ The implication relation between variable assignment from constraint clause PIG of the propagation a = 1 Clause set: ∪ 𝑐 , ¬ ∪ 𝑑, ¬𝑑 ∪ 𝑒, ¬ ∪ 𝑑 1𝑡𝑢 𝐶𝐷𝑄, = 1 → 𝑑, ¬𝑑 ∪ 𝑒 𝑠𝑓𝑛 𝑗𝑜 c = 1 ¬𝑑 ∪ 𝑒 2𝑜𝑒 𝐶𝐷𝑄, 𝑑 = 1 → 𝑒 𝑠𝑓𝑛 𝑗𝑜 d = 1 https://en.wikipedia.org/wiki/Unit_propagation 19/47

(3) I NITIAL P ROPAGATION ▪ Layout Structure Map (L) → Estimated Conflict Range Power Rail 0 1 2 7 9 12 4 3 1 • #V_Tracks= 9 2 • #H_Tracks= 13 • PinDensity= 100% 3 4 • 14 Pins : 0-13 5 • 8 Outer Pins : 14-21 6 • 10 Nets : {1 7 18}, {2 6 20}, 7 {3 10}, {13 19}, {9 12}, {4 17}, 8 {8 14}, {0 16}, {5, 15}, {11 21} 9 10 11 Estimated Conflict Region 10 13 8 11 5 6 0 12 0 1 2 3 4 5 6 7 8 20/47

(4) DLS (D ECISION WITH L ONGEST - PATH S EARCH ) ▪ Longest-path search is most comprehensive explanation about failure ▪ Via Position / Direction of Element are determined at DLS phase Blocked via (M 1 ↔ M 2 ) Selected ! 0 1 2 7 9 12 4 3 1 2 7 9 12 4 3 1 2 7 9 12 4 3 1 2 3 4 5 6 Conflict @ 4th Conflict @ 2nd Conflict @ 1st 7 8 9 10 11 10 13 8 11 5 6 0 10 13 8 11 5 6 0 10 13 8 11 5 6 0 12 0 1 2 3 4 5 6 7 8 21/47

(5) P ROPAGATION – PTA ( WITH T RUE A SSIGNMENT ) ▪ BCP propagation with True Assignment (U s ) 𝑁 2 𝑤 𝑉 (3) (1) 𝑄𝑗𝑜 𝑘 → 𝑁 1 (2) 𝑊𝐽𝐵 (𝑁 1 → 𝑁 2 ) 𝑤 𝐶 (2) 𝑁 1 (3) 𝑁 2 𝑤 𝑤 𝐺 (1) 𝑄𝑗𝑜 𝑘 (𝑇𝑣 𝑓𝑠𝑜𝑝𝑒𝑓) 22/47

(5) P ROPAGATION – PTA ( WITH T RUE A SSIGNMENT ) ▪ PTA Result of #1 VIA @ 9_13_100 0 1 2 7 9 12 4 3 1 𝐵𝑡𝑡𝑗𝑕𝑜𝑓𝑒 𝐺 𝑚𝑡𝑓 2 3 4 5 𝑛 3,10,1 ,(3,10,2) = 1 6 𝑊𝑆 (𝑇𝑢 𝑑𝑙𝑓𝑒) 𝑊𝑆 𝑊𝑆 7 𝑛 (3,10,2)(3,10,3) = 0 𝑛 (4,10,1)(4,10,2) = 0 8 𝑛 (4,9,1)(4,9,2) = 0 9 𝑁𝑇 𝑁𝑇 𝑁𝑇 10 6 9 9 𝑓 3,10,2 ,(3,10,3) = 0 𝑓 4,9,1 ,(4,9,2) = 0 𝑓 4,10,1 ,(4,10,2) = 0 11 10 13 8 11 5 6 0 𝐹𝐵 𝐹𝐵 12 𝐹𝐵 0 1 2 3 4 5 6 7 8 9 (4,9,1)(4,9,2) = 0 9 (4,10,1)(4,10,2) = 0 6 (3,10,2)(3,10,3) = 0 𝑔 𝑔 𝑔 0 0 0 Blocked via (M 1 ↔ M 2 ) Blocked via (M 2 ↔ M 3 ) Assigned via (M 1 ↔ M 2 ) 23/47