Revisions to Conventional Clock Domain Crossing Methodologies in - PowerPoint PPT Presentation

Revisions to Conventional Clock Domain Crossing Methodologies in Triple Modular Redundant Circuits Melanie Berg, AS&D in support of NASA/GSFC Melanie.D.Berg@NASA.gov Kenneth LaBel, NASA/GSFC 1 To be presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Acronyms Hold time (t h ) • • Application specific integrated circuit (ASIC) • Input – output (I/O) • Block random access memory (BRAM) • Linear energy transfer (LET) • Block Triple Modular Redundancy (BTMR) • Local triple modular redundancy (LTMR) • Clock (CLK or CLKB) • Mean Time between failure (MTBF) • Clock to output time (t co ) • NASA Electronic Parts and Packaging (NEPP) • Collected charge (Q coll ) • Negative doped with electrons (N + ) • Combinatorial logic (CL) • Operational frequency ( fs) • Computer aided design (CAD) • Power on reset (POR) • Configurable Logic Block (CLB) • Place and Route (PR) • Configuration cross section (P configuration ) Positive doped with holes (P + ) • • Critical charge (Q crit ) • Radiation Effects and Analysis Group (REAG) • Digital Signal Processing Block (DSP) • Set up time (t su ) • Distributed triple modular redundancy (DTMR) • Single event functional interrupt (SEFI) • Dual interlocked cell (DICE) • Single event functional interrupt cross section (P SEFI ) • Dual redundancy (DR) • Single event effects (SEEs) • Edge-triggered flip-flops (DFFs) • Single event latch-up (SEL) • Energy (E) • Single event transient (SET) • Equivalence Checking (EC) • Single event upset (SEU) • Error detection and correction (EDAC) Single event upset cross-section ( σ SEU ) • • Field programmable gate array (FPGA) • System cross section (P(fs) error ) • Finite state machine (FSM) Time delay ( τ dly ) • • Flip flop (DFF) • Voltage connected to positive rail (V DD ) Frequency of capture domain B (f clkB ) • • Voltage connected to ground rail (V SS ) • Frequency of incoming data (f DataA ) • Functional logic cross section (P functionalLogic ) • Gate Level Netlist (EDF, EDIF, GLN) • Hardware Description Language (HDL) 2 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Agenda • Metastability • Single Event Upsets (SEUs). • Triple modular redundancy (TMR). • Metastability filters and TMR. 3 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Metastability • Cause: Introducing an asynchronous signal into a synchronous (edge triggered) system... Or creating a combinatorial logic path that does not meet timing constraints. • Effect: – Flip-flop (DFF) clock captures signal during window of vulnerability. – DFF output Hovers at a voltage level between high and low, causing the output transition to be delayed beyond the specified clock to output (t CO ) delay. • Probability that the DFF enters a metastable state and the time required to return to a stable state varies on the process technology and on ambient conditions. • Generally the DFF quickly returns to a stable state. However, the resultant stable state is not deterministic 4 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Metastability Timing Diagram (Destination DFF) Source DFF Clock A Destination DFF Destination DFF Clock B D Q Input Output D Q D Q Setup time : t su Clock Hold time : t h Clock-to-Output : t co t h t su Clock Cause: Input violates t su t co Metastable output settles to new value after t co Effects: Metastable output settles to old value after t co 5 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Solution: Metastability Filter • Incoming signal is clocked in Domain A. Destination signals are clocked in Domain B. • • Filter: Use a capture DFF and at least one protection DFF. – Both DFFs are clocked in the capture domain. – The first DFF is expected to go metastable. – The second DFF is used to protect the rest of the system from potential metastable output. – However, there is no guarantee that the second DFF will not also become metastable. Metastability filters have a mean time between failure (MTBF). – Depends on slack time ( t slack ) between the metastability DFFs; process parameters ( c1 and c2 ); frequency of incoming data ( f DataA ); and frequency of capture domain ( f clkB ). clk B clk A D t slack/c2 e F MTBF = F c1×f DataA ×f clkB 6 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Slack Time (t slack ) between Metastability DFFs t slack t su clock Source DFF Data launch from DFF source D Q Combinatorial logic Data arrives at t dly DFF destination D Q Destination DFF • Nets and combinatorial logic add delay. t slack/c2 • Delay reduces slack time. e • Metastability filter rule: no combinatorial MTBF = logic between metastability filter DFFs; and c1×f DataA ×f clkB connection net length must be minimized. 7 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Device Penetration of Heavy Ions and Linear Energy Transfer (LET) • LET characterizes the deposition of charged particles. • Based on average energy (E) loss per unit path length (x) (stopping power). • Mass is used to normalize LET to the target material. VDD Off 2 1 dE Transistor is cm = LET MeV ; Susceptible ρ dx mg Density of target material Current Units Q coll > Q crit Flows through On Single event transient (SET) Collected charge Q coll Transistor Single event upset (SEU) Critical Charge Q crit 8 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

How SEUs Affect FPGAs • SEU and SET error signatures vary between FPGA devices: – Temporary glitch (transient) – Change of state (in correct state machine transitions) – Global upsets: Loss of clock or unexpected reset – Route breakage (no signal can get through) – Configuration corruption – Current jumps or increases (contention) Sequential and Glitches in System Configuration Combinatorial logic global Routes malfunction SEU that causes (CL) events in data and Hidden malfunction path Logic Triple modular redundancy (TMR): A common approach to SEU mitigation. 9 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

How To Insert TMR into A Design: TMR can be manually Functional written into the HDL. HDL Specification Generally not done because too difficult. Synthesis Output of synthesis is a Automated: TMR can gate-level netlist be inserted during that represents Place and Route synthesis or post the given HDL synthesis. function. If inserted post synthesis, the gate Create level netlist is Configuration replicated, ripped apart, and voters + feedback are inserted. HDL: Hardware description language 10 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

Various TMR Schemes: Different Topologies Block diagram of local Block diagram of block Block Diagram of TMR (BTMR): a complex TMR (LTMR): only flip- distributed TMR (DTMR): flops (DFFs) are function containing the entire design is combinatorial logic (CL) triplicated and data- triplicated except for the and flip-flops (DFFs) is paths stay singular; global routes (e.g., clocks); voters are brought into triplicated as three voters are brought into the black boxes; majority the design and placed design and placed after the in front of the DFFs. voters are placed at the flip-flops (DFFs). DTMR outputs of the triplet. masks and corrects most single event upsets (SEUs). 11 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

BTMR And Metastability clk B clk A D F F • Synchronize all signals prior to usage in BTMR copies. All three copies • This will require pulling out share clk B internal metastability filters contained in the each copy. 12 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

LTMR And Metastability D D D D Domain B F F F F cannot use F F F F signal until it is synchronized. Domain A Domain B Domain A Domain B Metastability filter LTMR: voter placed between metastability filters. Violation 13 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.

LTMR And Metastability t slack/c2 Mean time between failure (MTBF) e MTBF = C2 and C1 are process dependent constants. c1×f DataA ×f clkB f clkB is the capture clock domain frequency. f DataA is the maximum data switching frequency. One solution is to remove Voter placed between the voters between metastability filters. metastability DFFs Violation Another solution is to include additional DFFs in the metastability filter (increase t slack ) 14 Presented by Melanie Berg at the Hardened Electronics and Radiation Technology Conference, April 16-20, 2018, Tucson, AZ.