RapidIO Overview March 2014 Barry Wood, Chair, RapidIO Technical - PowerPoint PPT Presentation

RapidIO Overview March 2014 Barry Wood, Chair, RapidIO Technical Working Group barry.wood@idt.com OR twg-chair@rapidio.org

RapidIO Evolution Date Event Max Lane Speed Electricals 1997 Mercury Computer and Motorola (Freescale) begin to collaborate on a replacement for the Raceway interconnect 2000, RapidIO Trade Association March formed 2000, June RapidIO 1.2 (Parallel PHY) 1 Gbps LVDS, 8/16 bit bus 2003, Oct RapidIO 1.3 (Serial PHY) 3.125 Gbaud XAUI, 8b/10b Adopted as ISO standard (ISO/IEC DIS 18372) 2008 RapidIO 2.0 (Faster) 6.25 Gbaud OIF CEI, 8b/10b 2013 RapidIO 3.0 (Faster) 10.3125 Gbaud 10G-kr, 10G-ab 64b/67b 2015(?) RapidIO 4.0 (Faster) 25 Gbaud 64b/67b? • Over 6 million RapidIO switches shipped • Over 30 million 10-20 Gbps ports shipped > 10GbE March 2014 2

RapidIO Attributes Scalability Fault Tolerance Interoperable Power Efficiency Low Latency Any System Topology March 2014 3

Example System: ASML & Prodrive 100+ KW RapidIO Precision Power Supply Optics Control APPLICATION: Semiconductor photolithography machines 10,000 to 50,000 Hz control loop frequencies => nanometer precision https://www.youtube.com/watch?v=B9uDMNmajgw March 2014 4

Strong Ecosystem Axxia Communications DSP: several products Processor DSP , PowerQUICC & QorIQ multicore In TCI64xx family FPGA: Arria and Stratix Family FPGA: Virtex 4/5/6 families FPGA XLS416 family Switches, Bridges & IP Multicore CPS and Tsi Family Processor Wireless Baseband Processor DSP Oct22xx Network Processor Octeon 2 family Network Processor PowerPC based processors WinPath3 460GT Used by all of the top 10 Wireless OEMs March 2014 5

RapidIO Specification Structure (7) Interop (2) Message (5) Global (9) Flow Control Logical Shared Layer (1) Logical I/O Memory (8) Error (10) Data Streaming Management /Hot Swap Annex I Transport (11) Multicast (3) Transport HW API Layer System Bringup (12) VoQ Physical (4) Parallel PHY (6) Serial Backpressure Layer (Deprecated) Annex II Encapsulation March 2014 6

RapidIO Specification Mapped to Devices Hardware DSP DSP Logical Terminated uProc Switch Read/Write and DSP DSP Messaging Switch Transport CS Packet 0 CS CS Physical A B CS Packet 1 CS Packet 2 CS Packet 2 CS March 2014 7

Packet Exchange Protocol Packet Transfer Receiver-based Error Recovery Flow Control Rx Rx Tx Tx Rx Tx EOP RFR Packet 2 SOP Packet 1 SOP Packet 3 EOP EOP Reliable, In Order, Packet Delivery 31-4095 Outstanding Packets March 2014 8

Control Symbols Receive Side Transmit Side “Type 0” “Type 1” Control Symbol Type 0 Parm 0 Parm 1 Type1 CMD CRC Identifier Start-of-packet Packet Accepted Stomp Packet Retry End-of-packet Packet Not Accepted Restart-from-retry Status Link Request VC Status Multicast Event Link Response No Operation/Ignore Timestamp Timestamp Calibration 24, 48, or 64 bits March 2014 9

Packet Format Overview Physical Transport Logical 32,64 10 2 4 8,16,32 8,16,32 Physical Bits Logical Header TT FType Dest ID Src ID Control Symbol 16 16 32,64 Data Payload Early CRC Data Payload Final CRC Control Symbol 8 to 256 bytes Packets cannot be altered by RapidIO switches – CRC is constant. RapidIO Standard defines 9 Virtual Channels (guaranteed bandwidth) Virtual Channel 0 supports 4 or 8 priorities. March 2014 10

Topology and Routing End End Point Point End Point Switch End End End End Point Point Point Point Switch Switch Switch Switch Switch End End End End End End End End Point Point Point Point Point Point Point Point Star Dual Star Tree • RapidIO is topology agnostic End End Point Point Switch Switch • Packet DestinationID defines route • Routing is controlled through standard registers Switch Switch End End Point Point •DestinationID routing can be multicast or unicast Mesh within each switch March 2014 11

I/O System March 2014 12

I/O System Memory Mapping CPU2 CPU2 RapidIO Internal CPU1 Memory Memory Map Map Packet Physical Transport Logical 32,64 10 2 4 8,16 8,16 4 4 Control Symbol Physical Bits TT FType Dest ID Src ID Transaction Size 8 32, 48, 64 16 16 32,64 SrcTID Memory Address Data Payload Early CRC Data Payload Final CRC Control Symbol 8 to 256 bytes March 2014 13

Message Passing and Data Streaming Operation Transactions Possible System Usage Description Packet Format Used Doorbell DOORBELL, Event notification independent of source Part 2, Section FType 10 RESPONSE and target memory map implementation, 3.3.1 Section 4.2.4 efficient hardware implementation Logical Layer Retry Data MESSAGE, Message transfer independent of source Part 2, Section FType 11 Message MESSAGE and target memory map implementation, 3.3.2 Section 4.2.5 RESPONSE limited number of connections/queues, efficient hardware implementation Logical Layer Retry Data Data Streaming Message transfer independent of source Part 10, FType 9 Streaming Single Segment, and target memory map implementation. Section 3.2 Part 10, Start/Continue Connection oriented, 64K Section 4.2 /End Segments, connections/queues, support for Extended Header XON/XOFF, Rate and Credit based flow Flow Control control. No Logical Layer Retry March 2014 14

Type 10 Packet - Doorbell Request Packet Response Packet Request Packet Physical Transport Logical 10 2 4 8 8 16 16 Physical Bits TT FType Dest ID Src ID Rsvd TID Info Final CRC Response Packet 10 2 4 4 4 8 16 Physical Bits TT FType Dest ID Src ID TType Status TID Final CRC “STATUS” is “Retry” when the receive queue is full. March 2014 15

FType 9 – Data Streaming Start Segment Single Segment Cont Segment Cont Segment Max 64KB transfer, Cont Segment Byte granularity Cont Segment Start Segment End Segment End Segment March 2014 16

Data Streaming Flow Control Sources send Server Responds with Transmit Queue Status Flow Control Messages to Server Src 0 Src 0 Src 1 Server Src 1 Server Src 2 Src 2 Sources communicate queue fill level 3 Flow Control Protocols Supported: 000/255 means “Empty” and - XON/XOFF 255/255 means “Full” - Rate Based - Credit Based Flow Control can be applied to - A single Stream - A group of Streams - All Streams for a port March 2014 17

XON/XOFF Flow Control Sources send Server Responds with Transmit Queue Status Flow Control Messages to Server F E XON Src 0 Src 0 F E XOFF Src 1 Server Src 1 Server F E XON Src 2 Src 2 XON/XOFF - Service the fullest queue exclusively OR - Round robin among different queues OR - Use for “babbler” control March 2014 18

Rate Based Flow Control Sources send Server Responds with Transmit Queue Status Flow Control Messages to Server F E Dec 64/255 Src 0 Src 0 NoChange F E Src 1 Server Src 1 Server F E Inc 255/255 Src 2 Src 2 Rate Based - Increase rate by a fraction of current rate - Decrease rate by a fraction of current rate - XON - XOFF March 2014 19

Credit Based Flow Control Sources send Server Responds with Transmit Queue Status Flow Control Messages to Server <Low Prio> XOFF F E Src 0 Src 0 10 Credits left <All> 128 Cr F E Src 1 Server Src 1 Server <All> 255 Cr F E Src 2 Src 2 10 Credits left Credit Based - Allocate credits to one of up to 16 buckets - XON - XOFF March 2014 20

RapidIO System Discovery DSP 0 DSP 1 2 3 1 uProc Switch 4 5 DSP 3 DSP 2 System discovery uses a recursive algorithm to - Discover location and connectivity of all switches and endpoints - Allocate destination IDs to DSPs - Configure switch routing tables Discovery can be executed from any endpoint Standard system discovery supports two redundant hosts March 2014 21

RapidIO for Fault Tolerant Systems Data Processing System Host DSP DSP uProc Switch Switch DSP DSP Redundant System Host DSP DSP uProc Switch Switch DSP DSP • Detection “Fail-stop” Error • Isolation Management • Notification Support • Diagnosis • Recovery March 2014 22

RapidIO Form Factor & Connector Standards This Slide Intentionally Blank March 2014 23

New RapidIO Features for Space • It is possible to build Space systems with devices compliant to the RapidIO 1.x or 2.x specifications. • RapidIO Trade Association’s NGSIS Task Group is defining a profile of required features for Space compliant devices • Additional features for space operation are being defined. March 2014 24

RapidIO  SpaceWire/Fibre Bridging SpaceWire/Fibre Bridge Encapsulates RapidIO Packets RapidIO Packets Endpoint SpaceWire/Fibre Endpoint Bridge SpaceWire/Fibre RapidIO Endpoints only Endpoints process know about RapidIO RapidIO packets • In software • In hardware March 2014 25

RapidIO  SpaceWire/Fibre Bridging RapidIO Packets Encapsulate SpaceWire/Fibre Message Packets (4K) Data Streaming (64K) SpaceWire Implementation Specific Bridge Endpoint Endpoint SpaceFibre Read/Write (256 Bytes) Read/Write to Buffer SpaceWire/SpaceFibre RapidIO Endpoints Endpoints need only process know about SpaceWire/SpaceFibre SpaceWire/SpaceFibre packets • in software • in hardware March 2014 26