Configurable Cores: XTensa CSE 291E / EE260C Spring 2002
Overview • Overview of Tensilica • Overview of XTensa – Design Flow – Base ISA – Optional Components – TIE • Challenges for Customized Processors – What are the problems? – How does XTensa address them? – What could be done better? Tim Sherwood 2
Tensilica: The Company • Founder/CEO/Mastermind - Chris Rowen – from Intel, Stanford, MIPS, sgi, Synopsys • Idea: Build customizable processor design chain • Strategic Investors – Cisco, Matsushita, Altera, Conexent, NEC Tim Sherwood 3
Motivation: The “Design Gap” Tim Sherwood 4
Motivation: Before Tim Sherwood 5
Motivation: With XTensa Tim Sherwood 6
Design Flow - high level Tim Sherwood 7
Design Flow – detailed Tim Sherwood 8
Xtensa ISA Priorities • Code Size – Large factor in system cost • Configurability, Extensability – Provide match to requirements • Processor Cost – More than just area? • Energy Efficiency • Performance • Scalability • Features Tim Sherwood 9
Xtensa ISA • RISC architecture • 5-stage Pipeline – I R E M W • 24/16 bit instructions Tim Sherwood 10
Xtensa Pipeline Instruction Instruction Instruction I RAM Cache ROM R General CoProcessor Decode Registers Registers E Address ALU Generation CoProcessor ALU Data Data Data M XLMI ROM Cache RAM Instruction W ROM Tim Sherwood 11
XTensa Architecture Base ISA Configurable Optional Advanced Trace port JTAG Tap Optional & Configurable Control On-Chip Debug Instr Instruction Align and Decode TLB Cache Register File Instruction Fetch Unit Instruction ROM Designer ALU defined Instruction RAM Processor Controls register files Interupt Control Mul16 Timers 0 -n Mac16 Data Data TLB Cache Exception Control Designer Mul32 Data Defined Data ROM Load/Store Execution FPU Unit Units Data RAM Vectra DSP XLMI Data Address Watch 0 -n Instr Address Watch 0 -n Tim Sherwood 12
TIE • Major parts of TIE – Instruction Fields – Opcodes – Operands – State and Register – Instruction Semantics – Compiler Prototype – Pipelining/Scheduling • What do we need to worry about? Tim Sherwood 13
TIE Overiew • No micro-architecture details – Same TIE will work with new base – Decode, interlock, bypass, and pipelining, OS support of context switch automatic • Automatic configuration of software tools – Compiler – Instruction-set simulator – Debugger • Automatic Synthesis Tim Sherwood 14
TIE E xample: ADD4 Tim Sherwood 15
TIE E xample: Accum Tim Sherwood 16
Code Size • Small Encoding Size – 24/16 bits – Mode-less encoding • Code savings from elimination of save/restore – Special instruction now handles this – Estimate 6-10% Reduction in code size • Compound Instructions – Loop instructions / Compare-and-Branch – Shift-Add/Subtract – Shift-Mask Tim Sherwood 17
Instruction E ncoding Tim Sherwood 18
E xample Code Tim Sherwood 19
What are the challenges? • Layout / Synthesis • Code Size • Verification • Ease/Speed of use Tim Sherwood 20
Layout / Synthesis • Not Full Custom • One Clock – Rising Edge Triggered – No standard processor tricks • No time borrowing • Caches – Generated with memory compiler – Registered address input • Use hints to layout tools to make sure there is a sane placement Tim Sherwood 21
Code Size • Small instruction encoding • Compound instructions • Register Windows • Section/Pooling Literals • What else could we do? Tim Sherwood 22
Verification • Directed Diagnostics • Psuedo-Random program generator • Coverage Analysis – Architecture level (AVP) – Micro-architecture level (MVP) – Random generator – Cycle accurate simulator -> Co-simulation • What else? Tim Sherwood 23
E ase/ Speed of use Tim Sherwood 24
Conclusions and Discussion • What is next for Tensilica and Customized processors in the future? – CMP? – Vector? – FPGA based? – Tile based? – What about further out? Tim Sherwood 25
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