powering, CMS upgrade phase 2 Agathe Nidriche 26/07/2019 Agathe - PowerPoint PPT Presentation

Optimizing headroom for serial powering, CMS upgrade phase 2 Agathe Nidriche 26/07/2019 Agathe Nidriche – Optimization for the Headroom 1

SUMMARY I) Introduction II) Presentation of the modelisation III) 1 FE Chips simulation IV) Study : Best Configuration, 4 chips V) Study : Best Configuration, 2 chips Conclusion 26/07/2019 Agathe Nidriche – Optimization for the Headroom 2

I) Introduction : Headroom -We need to give headroom to each Shunt LDO to V prevent the module from powering shortages (increasing of the load (hitrate), chip failure, Rdig launching of the clock )……. Rana Vin nominal Voff Dig headroom Ana headroom (=unused current) (=unused current) -The current sharing (choice of R and Voff) must be I precise to get enough digital and analog headroom. Idig required Idig Iana required Iana -However giving more headroom means more 𝐽 = 𝐽 𝑒𝑗𝑕𝑠𝑓𝑟𝑣𝑗𝑠𝑓𝑒 ∗ (1 + Headroom dig ) + power consumption (since all the unused current is shunt to the ground). 𝐽 𝑏𝑜𝑏 𝑠𝑓𝑟𝑣𝑗𝑠𝑓𝑒 ∗ (1 + Headroom ana ) 26/07/2019 Agathe Nidriche – Optimization for the Headroom 3

I) Introduction : Headroom The headroom is the difference between the load consumed current and the input current. -Headroom for the analog SLDO -Headroom for the digital SLDO -Global Headroom 𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛 𝑏𝑜𝑏 = 𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛 𝑒𝑗𝑕 = 𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛 𝑕𝑚𝑝𝑐𝑏𝑚 = (𝐽 𝑡𝑣𝑞𝑞𝑚𝑧𝑏𝑜𝑏 −𝐽 𝑠𝑓𝑟𝑏𝑜𝑏 )/ 𝐽 𝑠𝑓𝑟𝑏𝑜𝑏 (𝐽 𝑡𝑣𝑞𝑞𝑚𝑧𝑒𝑗𝑕 −𝐽 𝑠𝑓𝑟𝑒𝑗𝑕 )/ 𝐽 𝑠𝑓𝑟𝑒𝑗𝑕 ( 𝐽 𝑡𝑣𝑞𝑞𝑚𝑧 - 𝐽 𝑠𝑓𝑟 )/ 𝐽 𝑠𝑓𝑟 Goal : get the best analog and digital headrooms for the lowest global headroom. 26/07/2019 Agathe Nidriche – Optimization for the Headroom 4

II) Presentation of the modelisation : Circuit 𝐽 𝑡𝑣𝑞𝑞𝑚𝑧 + ෍ 𝑊 𝑗 𝑆 𝑗 = V module ෍ 1 𝑆 𝑗 Analog Digital Analog Digital 𝑊 − 𝑊 𝑝𝑔𝑔 𝑇𝑀𝐸𝑃 SLDO SLDO SLDO SLDO 𝐽 𝑇𝑀𝐸𝑃 = 𝑆 𝑇𝑀𝐸𝑃 𝐽 𝑇𝑀𝐸𝑃 𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛 𝑇𝑀𝐸𝑃 = 𝐽 𝑠𝑓𝑟𝑣𝑗𝑠𝑓𝑒 -1 𝐽 𝑡𝑣𝑞𝑞𝑚𝑧 = (෍ 𝐽 𝑇𝑀𝐸𝑃 ) ∗ (1 + Headroom global ) Chip1 Chip2 Formula that caracterize the module 4-SLDOs module = 2-Chips module 26/07/2019 Agathe Nidriche – Optimization for the Headroom 5

II) Presentation of the modelisation : FE Chip One FE Chip One FE Chip = 1 analog and 1 digital part. Analog Digital SLDO SLDO Analog part requires 1.0 A Digital part requires 0.5 A . Chip level : We consider that one FE Chip is composed of 2 SLDOs with the same offsets and different slopes. Module level : We consider that each chip on the module is composed of the same SLDOs How can we chose the resistances and offsets of the Shunt LDOs such that each SLDO gets enough headroom ? 26/07/2019 Agathe Nidriche – Optimization for the Headroom 6

II) Presentation of the modelisation : Circuit working conditions For all simulations, we decide that the module works if it fits the considered conditions : - Vmodule>1,45V (a) -Vmodule<2V if one chip fails (b) -The headroom for the analog SLDO is over 10% (Headroom_ana>10%) -The headroom for the digital SLDO is over 10% (Headroom_dig>10%) This is one of the most basic scenarios concerning headroom issues, it underevaluates reality. >1,45V <2V Case (b) Case (a) 26/07/2019 Agathe Nidriche – Optimization for the Headroom 7

III) Simulation : 1 Chip, Voff=0.8V, 20% headroom Headroom_ Goal : find the values dig Headroom_ana<10% Allowed region <10% Ex : of resistances R_ana x=0.3, R=0.7 -> and R_dig for a fixed R_dig=0.91 M Ω Voff=0.8, 1, 1.2 V , that A_ana=0.49 M Ω enable the 1-chip- module to work in the previous conditions Headroom_dig (ie « Allowed region ») < 10% Headroom_ana<10% Vmodule<1,45V And And Vmod<1,45 V Vmod<1.45 V - Abscissa : x - Ordonnate : R -> - R_ana=(1-x)*R - R_dig=(1+x)*R 26/07/2019 Agathe Nidriche – Optimization for the Headroom 8

III) Simulation : 1 Chip, Voff=1V , 20% headroom Headroom_ Allowed Headroom_ana<10% dig <10% region - Abscissa : x - Ordonnate : R -> - R_ana=(1-x)*R - R_dig=(1+x)*R Headroom_dig < 10% Headroom_ana<10% Vmodule<1,45V And And Vmod<1,45 V Vmod<1.45 V 26/07/2019 Agathe Nidriche – Optimization for the Headroom 9

III) Simulation : 1 Chip, Voff=1.2V , 20% headroom Headroom_ana<10% Vfailure>2V And Vfailure>2V Allowed Headroom_ - Abscissa : x Headroom_ana<10% dig region - Ordonnate : R <10% -> - R_ana=(1-x)*R - R_dig=(1+x)*R Headroom_dig Headroom_ana<10% < 10% Vmodule<1,45V And And Vmod<1.45 V Vmod<1,45 V 26/07/2019 Agathe Nidriche – Optimization for the Headroom 10

IV) Study : Best Configuration, 4 chips : Allowed regions V_offset, V 1,2 1 0,8 25% Headroo m 20% 15% 26/07/2019 Agathe Nidriche – Optimization for the Headroom 11

IV) Study : Best Configuration, 4 chips : Power Limitation V_offset, V 1,2 1 0,8 25 % He adr 20 oo % m 15 % 26/07/2019 Agathe Nidriche – Optimization for the Headroom 12

IV) Study : Best Configuration, 4 chips : Resistance mismatch limitation. V_offset, V 1,2 1 0,8 25 % He adr 20 oo % m 15 % 26/07/2019 Agathe Nidriche – Optimization for the Headroom 13

IV) Study : Best Configuration, 4 chips : Offset mismatch limitation. V_offset, V 1,2 1 0,8 25 % He adr 20 oo % m 15 % 26/07/2019 Agathe Nidriche – Optimization for the Headroom 14

IV) Study : Best Configuration, 4 chips : 2 chips failure limitation. V_offset, V V_offset, V 1,2 1,2 1 1 0,8 0,8 25 25 % % Case of 2 chips failure : He He No resistances can enable the module adr adr to work for 0.8 offset voltage 20 20 oo oo (Works better for 1.2V than 1V). % % m m 15 15 % % 26/07/2019 Agathe Nidriche – Optimization for the Headroom 15

IV) Study : Best Configuration, 4 chips : Conclusion . V_offset, V 1,2 1 0,8 25% Headr oom 20% 15% Best offset value to work in every headroom conditions 26/07/2019 Agathe Nidriche – Optimization for the Headroom 16

IV) Study : Best Configuration, 4 chips : Conclusion. Optimal resistance Overlap values ([R_dig,R_ana]) for nominal work for 15% and 20% and 25% headroom : [0.966, 0.500] (M Ω ) 1 V offset 1 V offset 26/07/2019 Agathe Nidriche – Optimization for the Headroom 17

IV) Study : Best Configuration, 4 chips : Conclusion. Optimal resistance values ([R_dig,R_ana]) for nominal work for Overlap 15% and 20% and 25% headroom : [0.639, 0.350] (M Ω ) 1.2 V offset 1.2 V offset 26/07/2019 Agathe Nidriche – Optimization for the Headroom 18

V) Study : Best Configuration, 2 chips. Voffset 1 V 1.2 V 1V offset Overlap 25 % Headro om 20 % 1.2V offset Overlap 15 % 26/07/2019 Agathe Nidriche – Optimization for the Headroom 19

V) Study : Best Configuration, 2 chips. Voffset 1V 1.2V Power consumption,W Maximum tolerated percentage of mismatch, Voff. Maximum tolerated percentage of mismatch, resistance. 26/07/2019 Agathe Nidriche – Optimization for the Headroom 20

V) Study : Best Configuration, 2 chips: Conclusion. 26/07/2019 Agathe Nidriche – Optimization for the Headroom 21

Overall conclusion Optimal Range of Range of Headroom Tolerated Tolerated Voffset R_dig R_ana offset resistance mismatch mismatch Quadr Chip 1 V [0.4,0.8] [0.7,1.2] 15%-25% 4% 7% module Those two resistances are coupled. Double Chip 1.2 V [0.2,0.4] [0.45,0.65] 15%-25% 3.5% 8% module Those two resistances are coupled. 26/07/2019 Agathe Nidriche – Optimization for the Headroom 22

Backup Slides 26/07/2019 Agathe Nidriche – Optimization for the Headroom 23

Backup Slides : Different states of the module Chart : Different efficiency regions on the graph Region Headroom_dig<headro V_fail[j,i]>V_fail_max V[j,i]<Vmin Headroom_ana<headro om_threshold_dig om_threshold_ana Caracterization of the module efficiency 0 1 X 2 X 3 X X 4 X 5 X X 6 X X 7 X X X 8 X 9 X X 10 X X 11 X X X Pourcentage of discrepancy between slopes, x 12 X X 13 X X X 14 X X X 15 X X X X 26/07/2019 Agathe Nidriche – Optimization for the Headroom 24

Backup Slides : Simulation : 2 Chips, Voff=0.8V , 20% headroom Goal : find the values Headroom_dig< 10% Headroom_ana<10% of resistances R_ana Vfailure>2V And And and R_dig for a fixed Vfailure>2V Vfailure>2V And Voff=0.8, 1, 1.2 V , that Vfailure>2V and Two chips : Vmod<1.45 V Headroom_ana<10%, enable the 2-chips- Vmodule<1,45V 0.8 V offset isn’t Vfailure>2V module to work in the Vmod<1.45 enough to find previous conditions resistances that enable (ie « Allowed region ») a good sharing of the current Headroom_dig NO ALLOWED REGION - Abscissa : x < 10% Vmodule<1,45V Headroom_ana<10% And - Ordonnate : R And Vmod<1,45 V Vmod<1.45 V -> - R_ana=(1+x)*R - R_dig=(1-x)*R 20% headroom 26/07/2019 Agathe Nidriche – Optimization for the Headroom 25