Power and Energy Modelling of Multi-core Processors for System-Level Design Space Exploration Santhosh Kumar Rethinagiri, Oscar Palomar , Osman Unsal, Adrian Cristal Barcelona Supercomputing Center Energy-Aware Computing Workshop 2014 This project and the research leading to these results has received funding from the European Community's Seventh Framework Programme [FP7/2007-2013] under grant agreement n 318693
ParaDIME Consortium Cloud & Heat Technologies - Dresden TU – Dresden (GERMANY) (GERMANY) IMEC- Leuven (BELGIUM) University of Neuchatel (SWITZERLAND) BSC- Barcelona (SPAIN) 2 EACO Workshop, Sept. 10 th 2014, Bristol
Why ParaDIME ? Parallel Distributed Infrastructure for Minimization of Energy Rising cost Hardware cost Programming efficiency Runtime optimization Energy aware data center computing EACO Workshop, Sept. 10 th 2014, Bristol 3
The ParaDIME Stack ParaDIME Infrastructure Data Center Computing Node/Stack Computing Node/Stack TuD Application/BM Application/BM Multi Data Center Scheduler API API Scala Actor Sched Actor Sched Scala UNINE AKKA AKKA Cloud & Heat JVM JVM JVM JVM JVM JVM OS OS OS Technologies OS Simulated HW VM VM VM Accelerators Hyper Hypervisor BSC Cores Interconnect Real Real Real Real Real HW HW HW HW HW IMEC Future Devices Intra Data Center Scheduler EACO Workshop, Sept. 10 th 2014, Bristol 4
Challenges of modelling power of heterogeneous systems Estimating power/energy is a critical design goal for electronic devices. Designers today must evaluate power estimation as early as possible in the electronics design. Design changes are easier in the design phase and have the greatest impact on application power estimation at System-Level. A platform to use different processors and components . Functional level is accurate but it ’ s a course grain . Restriction in terms of measuring power from the real board. For fine grain , we can achieve it from gate level simulation. Restriction applies as we don ’ t have the tools and RTL sources. Very slow simulation speed. Another challenge is power law holds for a simple processor but for complex processor system remains debatable ? EACO Workshop, Sept. 10 th 2014, Bristol 5
Power estimation methodology and tools McPAT EACO Workshop, Sept. 10 th 2014, Bristol 6
Hybrid design space exploration methodology EACO Workshop, Sept. 10 th 2014, Bristol
First step : FLPA ( Functional Level Power Analysis) EACO Workshop, Sept. 10 th 2014, Bristol
Functional block (ARM Cortex-A9) EACO Workshop, Sept. 10 th 2014, Bristol
Generic Power Model Parameters The Parameters which influence the power in a system. EACO Workshop, Sept. 10 th 2014, Bristol
Power measurement environment Courtesy: Open-People project EACO Workshop, Sept. 10 th 2014, Bristol 11
Variation of Instruction Per Cycle (IPC) in Power for ARM Cortex-A8 Power� (mW)� 50� 45� 40� 35� (mW)� 30� Power� 25� 20� 15� 10� 5� 0� 0� 0.5� 1� 1.5� 2� Instruc on� Per� Cycle� (IPC)� EACO Workshop, Sept. 10 th 2014, Bristol
Power consumption models generated with FLPA EACO Workshop, Sept. 10 th 2014, Bristol
Second Step: System Level Power Analysis EACO Workshop, Sept. 10 th 2014, Bristol
Result Interface EACO Workshop, Sept. 10 th 2014, Bristol 15
Result Interface EACO Workshop, Sept. 10 th 2014, Bristol 16
Results and Comparison (Power estimation) EACO Workshop, Sept. 10 th 2014, Bristol
Results and comparison (Energy) EACO Workshop, Sept. 10 th 2014, Bristol
Third step: Auto optimization DVFS Runtime – Inter task DVFS Programmer annotation based DVFS Work-load balancing based on task Runtime Programmer based request EACO Workshop, Sept. 10 th 2014, Bristol 19
Task scheduling EACO Workshop, Sept. 10 th 2014, Bristol 20
Optimization based on work load balancing EACO Workshop, Sept. 10 th 2014, Bristol 21
Optimization (Inter task DVFS) EACO Workshop, Sept. 10 th 2014, Bristol 22
Conclusion In our tool, we have proved that our estimates are accurate. Adaptable for any kind of complex processor system. Added advantage, rapid prototyping of the components and porting of the applications made easy. Estimating power and designing applications made easy and time efficient. EACO Workshop, Sept. 10 th 2014, Bristol
The ParaDIME Stack ParaDIME Infrastructure Data Center Computing Node/Stack Computing Node/Stack TuD Application/BM Application/BM Multi Data Center Scheduler API API Scala Actor Sched Actor Sched Scala UNINE AKKA AKKA Cloud & Heat JVM JVM JVM JVM JVM JVM OS OS OS Technologies OS Simulated HW VM VM VM Accelerators Hyper Hypervisor BSC Cores Interconnect Real Real Real Real Real HW HW HW HW HW IMEC Future Devices Intra Data Center Scheduler EACO Workshop, Sept. 10 th 2014, Bristol 24
Hardware Architecture Energy-Efficient Message Passing Message passing microarchitecture Message passing accelerator Task passing Operation Below Safe V dd Automatic HW lowering of V dd SW-guided (low-power annotation) Errors? Heterogeneous Computing Architectural level Device level EACO Workshop, Sept. 10 th 2014, Bristol 25
Heterogeneous system-level environment PETS Tool activity counter Interface Task 3 Task 1 Task 2 ARM Cortex-A8 ARM Cortex-A9 DSP C64x Quad-core Quad-core ISS ISS ISS Bus Data FPGA Memory GPU accelerator Hardware Accelerator Virtual Platform EACO Workshop, Sept. 10 th 2014, Bristol 26
Heterogeneous computing results and comparison 1600 K-means 1400 1200 1000 Energy (J) 800 600 400 200 0 ARM Cortex-A9 ARM Cortex-A8 FPGA (ZynQ) DSP C64x GPU Tegra3 (quad core) (quad core) EACO Workshop, Sept. 10 th 2014, Bristol 27
Programming model Message passing programming model Actor model (Akka+Scala) Annotations to provide information to the hardware Operation below Safe Vdd Approximate Computing @ Storage(Array("precise=false", "VF_relax=true")) var x = 5 @Calculation(Array("VF_relax=true", "VF_det=DMR", VF_corr=TM")) def calc(first:Array[double]) Rewrite/Expand annotated code with Scala Macro Annotations EACO Workshop, Sept. 10 th 2014, Bristol 28
Power and Energy Modeling of Multi-core Processors for System-Level Design Space Exploration Oscar Palomar (BSC) Energy-Aware Computing Workshop 2014 This project and the research leading to these results has received funding from the European Community's Seventh Framework Programme [FP7/2007-2013] under grant agreement n 318693
Computation of power and measurement of voltage for OMAP EACO Workshop, Sept. 10 th 2014, Bristol
Power measurement environment EACO Workshop, Sept. 10 th 2014, Bristol
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