Plan 1 Goals 2 A First Try at RISC - V 3 Design Flow 4 - PowerPoint PPT Presentation

RISC - V design using FOSS Jean-Paul C HAPUT LIP 6, Sorbonne Université CIAN Team Marie-Minerve L OUËRAT , Roselyne C HOTIN , Jean-Paul C HAPUT , Adrian S ATIN Jean-Paul.Chaput@lip6.fr Paris, October 2 nd , 2019 This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 1 / 21

Plan 1 Goals 2 A First Try at RISC - V 3 Design Flow 4 Introduction to Symbolic Layout 5 Description of the Design Flow 6 Demo Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 2 / 21

Goals ✏ Taking the next step for an open processor. ✏ Give the ability to publish, share and modify the hardware design down to the layout. ✏ Increase security. ✏ Ensure the continued existence of the hardware. Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 3 / 21

Goals RISC - V design using FOSS 2019-09-30 Goals Goals ✏ Taking the next step for an open processor. ✏ Give the ability to publish, share and modify the hardware design down to the layout. ✏ Increase security. ✏ Ensure the continued existence of the hardware. • It seems only natural for a free and open processor to be built using free tools. • By checking the layout, we can better detect hardware trojan and ensure the chip is exactly what it is. • We expect FOSS to have the same e ff ect of community building. • NASA was forced to scavenge 8086 on eBay for the space shuttle around 2002 .

Implemented RISC - V ISA ✏ RV32I user-space ISA only. ✏ Target node will be AMS 350nm, 4 metal layers. Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 4 / 21

Implemented RISC - V ISA RISC - V design using FOSS 2019-09-30 A First Try at RISC - V ✏ RV32I user-space ISA only. ✏ Target node will be AMS 350nm, 4 metal layers. Implemented RISC - V ISA • We choose to start with as small possible a component. Always better for debugging... • Use of a mature node so not too expensive and not too much features to implement in the tools.

Architecture of our RISC - V IFETCH DEC EXE MEM WB Calcul next PC adder FIFO DEC to IFETCH Comparators −= − < S/U shifter Comparator DECOD logic < S/U FIFO EXE to MEM FIFO DEC to EXE FIFO MEM to WB Request LOGIC MEM BYPASSs INST to and byte select or memory and xor sign propagation MAE Request data FIFO IFETCH to DEC to memory bypass value REGISTERs Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 5 / 21

Architecture of our RISC - V RISC - V design using FOSS 2019-09-30 IFETCH DEC EXE MEM WB Calcul next PC adder FIFO DEC to IFETCH A First Try at RISC - V Comparators −= − < S/U shifter Comparator DECOD logic < S/U FIFO DEC to EXE FIFO EXE to MEM FIFO MEM to WB Request LOGIC MEM BYPASSs INST to and byte select or memory and xor sign propagation MAE Request data FIFO IFETCH to DEC to memory bypass value REGISTERs Architecture of our RISC - V • A simple five stage pipeline. • Based on our experience over the design of the MIPS R3000. • I’m not the architect, so I couldn’t answer tricky design questions...

What Do We Want to Do ? ENTITY halfadder IS PORT ( a : in BIT; b : in BIT; cin cout : out BIT; sout : out BIT; sout a ); END halfadder_x2; b ARCHITECTURE behaviour OF halfadder IS BEGIN cout sout <= (a xor b); cout <= (a and b); END; netlist layout RTL Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 6 / 21

What Do We Want to Do ? RISC - V design using FOSS 2019-09-30 ENTITY halfadder IS PORT ( Design Flow a : in BIT; b : in BIT; cin cout : out BIT; sout : out BIT; sout ); a END halfadder_x2; b ARCHITECTURE behaviour OF halfadder IS BEGIN cout sout <= (a xor b); cout <= (a and b); END; What Do We Want to Do ? RTL netlist layout • RTL toward netlist is «logical synthesis». • netlist toward layout is «physical synthesis».

General Outline of a VLSI Design Flow Cell RTL library Generators Migen Chisel SpinalHDL Logical Physical symbolic RTL synthesis netlist synthesis symbolic to real layout vhdl vhdl yosys Cadence vlog vlog ap s2r abc Coriolis real validation validation validation layout gds https://www.chisel-lang.org/ Chisel https://github.com/SpinalHDL/ SpinalRTL https://m-labs.hk/gateware/migen/ Migen Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 7 / 21

General Outline of a VLSI Design Flow RISC - V design using FOSS Cell 2019-09-30 RTL library Generators Migen Design Flow Chisel SpinalHDL Logical Physical symbolic RTL synthesis netlist synthesis symbolic to real layout vhdl vhdl yosys Cadence vlog vlog ap s2r abc Coriolis real validation validation validation layout gds General Outline of a VLSI Design Flow https://www.chisel-lang.org/ Chisel https://github.com/SpinalHDL/ SpinalRTL https://m-labs.hk/gateware/migen/ Migen • A word about HDL languages, for now we did it the old way in VHDL . C HISEL and S PINAL HDL have a logic more suited for programmers than computer scientists or electronic people. M IGEN is better and written in Python but do not generate VHDL (yet ?). All of them are difficult to extend if an unsupported feature occurs. • The LIP 6 contribution to the fl ow is mostly focused on the physical design stage. • More tools exists for the stage before because they can also target FPGA s. • The equal size of the boxes do not re fl ect on the hardness of each stage... • The last step, with S 2 R will be explained shortly thereafter.

A brief history of symbolic layout (1/2) Symbolic Mead & Conway λ 1 λ 0.5 µ = µ m 4 λ µ 2 µ 1 2 λ METAL2 metal2 µ m λ symbolic real layout layout ap GDS Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 8 / 21

A brief history of symbolic layout (1/2) RISC - V design using FOSS Symbolic Mead & Conway λ 1 λ 0.5 µ = µ m 2019-09-30 Introduction to Symbolic Layout 4 λ µ 2 µ 1 2 λ A brief history of symbolic layout (1/2) METAL2 metal2 µ m λ symbolic real layout layout ap GDS • Invented in 1980 by M EAD & C ONWAY . Draw your layout using a special dimension unit, the λ . Then scale to the target node. Assume that the shrink rate is almost the same for all layers. • Designed to cross the boundaries of foundries and nodes. • Allows a drastic reduction in the number of design rules. • Main drawback : the area loss, about 10%. • At the origin of MOSIS . • Simple shrink finally proven a little bit too rigid.

A brief history of symbolic layout (2/2) Symbolic Alliance λ 1 λ 0.5 µ = µ m δ e 4 λ 2 λ δ w METAL2 µ m λ symbolic real layout layout ap GDS Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 9 / 21

A brief history of symbolic layout (2/2) RISC - V design using FOSS Symbolic Alliance λ 1 λ 0.5 µ = µ m 2019-09-30 δ e Introduction to Symbolic Layout 4 λ 2 λ δ w A brief history of symbolic layout (2/2) METAL2 µ m λ symbolic real layout layout ap GDS • Refined by B ULL , to give A LLIANCE symbolic. Add cap and width extensions to give more slack in the transformation process. • B ULL is fabless and did not want to be tied to one foundry but didn’t want to develop twice it’s designs. • Has a big advantage unforeseen at the time, it is NDA free but still very close the the real layout. • So, layout is publishable and can be verified against what comes back from the foundry. Can be critical for security.

symbolic vs. real layout Free Under NDA design rules rds Symbolic to real symbolic layout ap s2r real layout GDSII Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 10 / 21

symbolic vs. real layout RISC - V design using FOSS 2019-09-30 Free Under NDA Introduction to Symbolic Layout design rules rds Symbolic to real symbolic layout ap s2r real layout GDSII symbolic vs. real layout • The translation from symbolic to real layout is ensured by the S 2 R program. It needs a parametrisation for the target node. • We are working for a way to provide this file (and some more) to other users through the M Y CMP service. • We keep as much as possible of the toolchain on the «left side»... • This is more di ffi cult when it comes down to timing informations and extraction. • The other way around NDA has been taken by F REE PDK, which develop fake but realistic design kits. Still they are made mainly for commercial tools.

Simulation Plateform with GHDL 0 1 good bad VHDL C RISC−V core Memory 1 inst_req 1 Stack inst_valid I−Cache 32 inst_adr 32 inst_in ck reset_n 1 data_load_w ELF 1 data_store_w 1 data_store_h 1 Data Data data_store_b D−Cache 32 data_adr 32 data_out 32 data_in Code Code 1 data_valid Oct 2 nd , 2019 J.-P. C HAPUT (SU-LIP6) RISC - V design using FOSS 11 / 21