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Pipelining Performance Measurements Cycle Time: Time in between - PowerPoint PPT Presentation

Mar 13, 2023 •325 likes •1.45k views

Pipelining Performance Measurements Cycle Time: Time in between clock ticks Latency: Time to finish a complete job, start to finish Throughput: Average jobs completed per unit time CyclesPerJob: Number of cycles between

  1. MEM IF ID WB or $s3, $s4, $t3 sw $s2, 0($t1) lw $s1, 0($t0) IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM or $s3, $s4, $t3 IF ID 1 2 3 4 5 6 7 8 Time->

  2. MEM IF ID WB or $s3, $s4, $t3 sw $s2, 0($t1) IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM 1 2 3 4 5 6 7 8 Time->

  3. MEM IF ID WB or $s3, $s4, $t3 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  4. MEM IF ID WB The machine in cycle 4 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  5. MEM IF ID WB The machine in cycle 5 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  6. In what cycle was $s1 written? In what cycle was $s4 read? In what cycle was the Add executed? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  7. In what cycle was $s1 written? 6 In what cycle was $s4 read? In what cycle was the Add executed? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1 , 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  8. In what cycle was $s1 written? 6 In what cycle was $s4 read? 5 In what cycle was the Add executed? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4 , $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  9. In what cycle was $s1 written? 6 In what cycle was $s4 read? 5 In what cycle was the Add executed? 3 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  10. Performance Analysis • Measurements related to our machine • Job = single instruction • Latency: Time to finish a complete _______________, start to finish. • Throughput: Average ______________ completed per unit time. • Which is more important for reducing program execution time?

  11. Performance Analysis • Measurements related to our machine • Job = single instruction • Latency: Time to finish a complete instruction start to finish. • Throughput: Average ______________ completed per unit time. • Which is more important for reducing program execution time?

  12. Performance Analysis • Measurements related to our machine • Job = single instruction • Latency: Time to finish a complete instruction start to finish. • Throughput: Average number of instructions completed per unit time. • Which is more important for reducing program execution time?

  13. Pipelined Machine Decode Execute Memory Fetch << << 4 2 2 Addr Out Data src1 src1data op/fun PC Read Addr Out Data rs Data Memory src2 src2data Instruction rt Register File Memory rd destreg imm In Data destdata Sign 16 32 Ext (Writeback) Pipeline Register

  14. Pipeline Registers • Named for two stages they separate • Store all data corresponding to lines that go through them w IF/ID w EX/MEM § 32b instruction § Zero § 32b nPC § 32b ALU result § 32b nPC w ID/EX § 32b register value § 32b register w MEM/WB § 32b register § 32b immediate field § 32b ALU result § 32b nPC § 32b memory value

  15. Register File • Only takes half of a cycle to read or write to register file • Convention: w Read 2nd half of cycle w Write 1st half of cycle

  16. Machine Comparison Fetch Decode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  17. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  18. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: _____ inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  19. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  20. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: 2.1 ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  21. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: 2.1 ns Latency of a single instruction: 2.1*5=10.5 ns Throughput for machine: _____ inst/ns

  22. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: 2.1 ns Latency of a single instruction: 2.1*5=10.5 ns Throughput for machine: 1 / 2.1 inst/ns

  23. Example 2 – How do we speed up pipelined machine? Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  24. Example 2 – How do we speed up pipelined machine? Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Single cycle: 1 / 32 inst / ns Pipelined: 1 / 10.1 inst / ns

  25. Example 2 – Split more stages Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Which stage(s) should we split? _________ and _________

  26. Example 2 – Split more stages Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Which stage(s) should we split? Memory and _________

  27. Example 2 – Split more stages Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Which stage(s) should we split? Memory and Execute

  28. Example 2 – After Split F D X1 X2 M1 M2 WB ___ns ___ns ___ns ___ns ___ns ___ns ___ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  29. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns ___ns ___ns ___ns ___ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  30. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns ___ns ___ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  31. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns 5 ns 5 ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  32. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns 5 ns 5 ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / 32 ns Pipelined: 1 / ns

  33. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns 5 ns 5 ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / 32 ns Pipelined: 1 / 6.1 ns

  34. Incorrect Execution Easy Right? Not so fast. In what cycle does the add write $s0? In what cycle does the or read $s0? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  35. Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  36. Easy Right? Not so fast. In what cycle does the add write $s0 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 3 IF ID MEM WB WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  37. Easy Right? Not so fast. Ahhhh! Values can not pass backwards in time In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 3 IF ID MEM WB WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  38. Correct, Slow Execution Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 5 Stall - wasted cycles IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 IF IF sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  39. Only Register File rd/wr in half a cycle. All Correct, Slow Execution other stages take a full cycle – this is because of shared hardware Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 5 Stall - wasted cycles IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 IF IF sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  40. Barriers to pipelined performance • Uneven stages • Pipeline register delays

  41. Barriers to pipelined performance • Uneven stages • Pipeline register delays • Data Hazards

  42. Barriers to pipeline performance • Uneven stages • Pipeline register delays • Data Hazards w An instruction depends on the result of a previous instruction still in the pipeline

  43. Solutions? • What can we try to reduce data hazards or their effect?

  44. Default (do nothing): Stall Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 5 Stall - wasted cycles IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 IF IF sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  45. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? In what cycle is $s0 used in the machine? IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  46. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? End of cycle 4 In what cycle is $s0 used ? IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  47. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? End of cycle 4 In what cycle is $s0 used ? beginning of cycle 4 IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  48. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? end of cycle 4 In what cycle is $s0 used ? beginning of cycle 5 IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 ID sw $s2, 0($t1) IF ID MEM WB IF and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  49. Data-Forwarding Where are those wires? Decode Execute Memory Fetch << << 4 2 2 Addr Out Data src1 src1data op/fun PC Read Addr Out Data rs Data Memory src2 src2data Instruction rt Register File Memory rd destreg imm In Data destdata Sign 16 32 Ext (Writeback) Pipeline Register

  50. Data-Forwarding Where are those wires? Decode Execute Memory Fetch << << 4 2 2 Addr Out Data src1 src1data op/fun PC Read Addr Out Data rs Data Memory src2 src2data Instruction rt Register File Memory rd destreg imm In Data destdata Sign 16 32 Ext (Writeback) Pipeline Register

  51. Data Forwarding Example 2 Draw the timing diagram with data forwarding Draw arrows to indicate data passing through forwarding lw $t0, 0($s0) F D M W addi $t0, $t0, 1 F D add $s2, $s2, $t0 F sw $s2, 0($s0) 1 2 3 4 5 6 7 8 9 10 11 12 Time->

  52. Solution 2: Instruction Reordering (Before reordering) Stall - wasted cycles IF ID MEM WB lw $s0, 0($t4) IF MEM WB or $s3, $s0, $t3 IF IF ID sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  53. Solution 2: Instruction Reordering (After Reordering) IF ID MEM WB WB lw $s0, 0($t4) IF ID MEM WB sw $s2, 0($t1) and $s6, $s4, $t3 IF ID MEM WB or $s3, $s0, $t3 IF ID ID MEM WB 1 2 3 4 5 6 7 8 Time->

  54. Who reorders instructions? • Static scheduling w Compiler w Simpler, but does not know when caches miss or loads/stores are to the same locations • Dynamic scheduling w Hardware w More complicated, but has all knowledge

  55. Solution 2: Instruction Reordering IF ID MEM WB WB lw $s0, 0($t4) IF ID ID MEM WB or $s3, $s0, $t3 sw $s3, 0($t1) IF ID MEM WB and $s0, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

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