Physical Design Considerations of One-level RRAM-based Routing Multiplexers Xifan Tang, Edouard Giacomin, Giovanni De Micheli and Pierre-Emmanuel Gaillardon March 20 th , 2017 For ISPD’17
Motivation ▲ Resistive Memory (RRAM) technology can offer ▽ Low on-resistance: source of high-performance ▽ Resistance independent from V DD : source of low-power ▲ Challenges in RRAM-based multiplexer design ▽ Co-integration of low-voltage V DD and high-voltage V prog ● V prog for RRAM programming circuits ● V DD for datapath circuits ▽ Eliminate crosstalk current between datapath and programming structures ▽ Consider physical design aspects ● Multiple wells, parasitic capacitances and physical location of RRAMs 2
Resistive Memory ▲ Fabrication ▽ Sandwiched structure ▽ Compatible with BEoL ▽ Between metal layers ▲ Two stable resistance states ▽ Filamentary conducting ▽ H igh R esistance S tate (HRS) ▽ L ow R esistance S tate (LRS) ▲ Adjustable set process ▽ Large Iset => Low LRS 3
4T1R Programming Structure ▲ 4T(ransistor)1R(RAM) programming structure ▽ 1.4x larger in programming current than 2T1R ▽ Achieve smaller LRS ▲ Set and Reset are controlled by two pairs of programming transistors independently Deep N-Well V prog V prog I reset P2 P1 V set,ENb I set V reset,ENb datapath,out datapath,in - + V reset,EN V set,EN C P N1 N2 GND GND [1] X. Tang et al., “A Study on the Programming Structures for RRAM-Based FPGA Architectures ,” IEEE TCAS-I, 4 Vol. 63, No. 4, pp. 503-516, April 2016.
Potential of RRAM-based Multiplexers ▲ High-performance ▽ Small capacitance on critical path ▲ Low power ▽ RRAM LRS is independent from V DD CMOS MUX: C path = (2 n + 1) C trans RRAM MUX: C path =2C prog,trans + N·C P 5
Naïve 4T1R-based Multiplexer ▲ Limitation 1: Programming current contribution from datapath inverters (Red arrows) Deep N-Well Regular Well Regular V DD,well Input inverters V DD,well Well P0 V DD A P1 BL[0] BL[N] R 0 in[0] - + Output Metal WL[0] inverter C P,0 N1 wire GND V DD GND,well group2 Metal B ... wire ... out group1 V DD,well V DD C P2 BL[N-1] GND R N-1 in[N-1] N0 - + WL[N-1] WL[N] N2 C P,N-1 GND GND,well GND,well programming current crosstalk current 6
Naïve 4T1R-based Multiplexer ▲ Limitation 2: Breakdown threats of datapath transistors (highlighted in red) ▽ Deep N-well V DD,well (3.0V) >> Regular Well V DD (0.9V) Deep N-Well Regular Well Regular V DD,well Input inverters V DD,well Well P0 V DD A P1 BL[0] BL[N] R 0 in[0] - + Output Metal WL[0] inverter C P,0 N1 wire GND V DD GND,well group2 Metal B ... wire ... out group1 V DD,well V DD C P2 BL[N-1] GND R N-1 in[N-1] N0 - + WL[N-1] WL[N] C P,N-1 N2 GND GND,well GND,well 7 programming current crosstalk current
Naïve 4T1R-based Multiplexer ▲ Limitation 3: Long interconnecting wires between deep N-well and regular well ▽ Large parasitic resistances and capacitances Deep N-Well Regular Well Regular V DD,well Input inverters V DD,well Well P0 V DD A P1 BL[0] BL[N] R 0 in[0] - + Output Metal WL[0] inverter C P,0 N1 wire GND V DD GND,well group2 Metal B ... wire ... out group1 V DD,well V DD C P2 BL[N-1] GND R N-1 in[N-1] N0 - + WL[N-1] WL[N] C P,N-1 N2 GND GND,well GND,well 8 programming current crosstalk current
Improved 4T1R-based Multiplexer ▲ Address limitations of naïve design ▽ Cut off programming current from datapath inverters ▽ Avoid transistor breakdown ▽ Short interconnecting wires Regular Well Deep N-Well Regular Deep N-Well Regular V DD V DD,well Input inverters V DD,well V DD V DD,well Well Well P0 V DD A P1 EN BL[0] BL[N] R 0 BL[0] BL[N] R A in[0] - in[0] + Output Metal - + WL[0] inverter N1 C P,0 wire WL[0] GND C P,A EN V DD,well GND,well V DD group2 Metal GND B ... Metal wire GND ... … … out wire out group1 V DD,well V DD V DD group 1 V DD C P2 EN BL[N-1] GND R N-1 GND well in[N-1] BL[N-1] R B N0 - + WL[N-1] WL[N] in[N-1] - + C P,N-1 N2 GND WL[N-1] WL[N] GND,well GND,well C P,B EN GND programming current crosstalk current GND GND well 9
Improved 4T1R-based Multiplexer ▲ Three modes: ▽ Operating: V DD,well = V DD , GND well = GND ▽ Set RRAM: V DD,well = -V prog + 2V DD , GND well = -V prog +V DD ▽ Reset RRAM: V DD,well = V prog , GND well = V prog -V DD (b) Deep N-Well Deep N-Well Deep N-Well (a) (c) V DD V DD V DD -V prog + 2 V DD V DD V prog V DD V DD V DD P0 EN EN EN R A BL[0] BL[N] BL[0] BL[N] BL[0] BL[N] R A in[0] in[0] in[0] - + - - + + WL[0] WL[0] WL[0] C P,A -V prog + 2 V DD V prog C P,A V DD EN EN EN GND GND GND GND GND GND … … … … out … … out out V DD V DD V DD V DD V DD V DD EN EN -V prog +V DD EN V prog -V DD GND BL[N-1] BL[N-1] R B BL[N-1] N0 in[N-1] - + in[N-1] - + + - in[N-1] WL[N] WL[N-1] WL[N] WL[N-1] WL[N] WL[N-1] C P,B C P,B EN EN EN GND -V prog +V DD GND GND GND V prog -V DD GND GND GND programming current 10
Improved 4T1R-based Multiplexer ▲ Advantage 1: zero programming current from datapath inverters ▽ Power-gated input inverters Regular Deep N-Well V DD V DD V DD,well Well EN BL[0] BL[N] R A in[0] - + WL[0] C P,A EN V DD,well GND Metal GND … … wire out V DD V DD group 1 EN GND well BL[N-1] R B in[N-1] - + WL[N-1] WL[N] C P,B EN GND GND GND well 11
Improved 4T1R-based Multiplexer ▲ Advantage 2: datapath transistors are protected from high programming voltages ▽ Large voltage difference shifts from transistors to RRAMs ▽ Allow to use standard transistors in programming structures ● Higher density and smaller transistor capacitances! (b) Deep N-Well Deep N-Well Deep N-Well (a) (c) V DD V DD V DD -V prog + 2 V DD V DD V prog V DD V DD V DD P0 EN EN EN R A BL[0] BL[N] BL[0] BL[N] BL[0] BL[N] R A in[0] in[0] in[0] + - - - + + WL[0] WL[0] WL[0] C P,A -V prog + 2 V DD C P,A V DD V prog EN EN EN GND GND GND GND GND GND … … … … out … … out out V DD V DD V DD V DD V DD V DD EN EN -V prog +V DD EN V prog -V DD GND BL[N-1] BL[N-1] R B BL[N-1] N0 in[N-1] - + in[N-1] - - + + in[N-1] WL[N] WL[N-1] WL[N] WL[N-1] WL[N] WL[N-1] C P,B C P,B EN EN EN GND -V prog +V DD GND GND GND V prog -V DD GND GND GND programming current 12
Improved 4T1R-based Multiplexer ▲ Advantage 3: only one interconnection between regular and deep N-wells ▽ Smaller parasitic capacitances! Regular Well Deep N-Well Regular Deep N-Well Regular V DD V DD,well Input inverters V DD,well V DD V DD,well Well Well P0 V DD A P1 EN BL[0] BL[N] R 0 BL[0] BL[N] R A in[0] - in[0] + Output Metal - + WL[0] inverter N1 C P,0 wire WL[0] GND C P,A EN V DD,well GND,well V DD group2 Metal GND B ... Metal wire GND ... … … out wire out group1 V DD,well V DD V DD group 1 V DD C P2 EN BL[N-1] GND R N-1 GND well in[N-1] BL[N-1] R B N0 - + WL[N-1] WL[N] in[N-1] - + C P,N-1 N2 GND WL[N-1] WL[N] GND,well GND,well C P,B EN GND programming current crosstalk current GND GND well 13
Improved 4T1R-based Multiplexer ▲ Advantage 3: only one interconnection between regular and deep N-wells (Cross-section View) ▽ Smaller parasitic capacitances! Well spacing: L (a) MET2 VIA VIA RRAM VIA MET1 WL[N] WL[0] CON BL[N] BL[0] CON in[0] CON V DD,well V prog GND well V DD in[0] V DD out GND GND TACT TACT TACT N+ N+ N+ P+ P+ N+ P++ P++ N+ P+ P+ N++ P+ P+ N+ P++ N++ N+ P+ P+ N+ N+ P++ P-Well P-Well N-Well Deep N-Well Well spacing: L MET2 (b) y x VIA RRAM MET1 MET1 in[0] WL[0] BL[N] BL[0] WL[N] GND well CON CON CON GND in[0] V DD V DD,well V DD,well GND out TACT TACT TACT N+ N+ P++ N+ P+ P+ P+ P+ N+ P++ N++ P+ P+ N+ P+ P+ N++ N++ N+ N+ P++ N+ N-Well P-Well Deep N-Well 14 P-Well
Improved 4T1R-based Multiplexer ▲ Share deep N-wells between cascaded multiplexers ▽ CMOS logic gates can locate in deep N-wells M inA[0] inB[0] M U ... U outA X outB ... X 0 inA[N-1] CMOS logic gates 1 inB[N-1] V DD,well V DD V DD Deep N-Well V DD,well V DD V DD,well EN EN BL[0] BL[N] BL[0] BL[N] inA[0] inB[0] - + + - WL[0] V DD WL[0] V DD,well EN EN GND ,well GND GND ,well GND outA … … … … outB V DD,well V DD V DD V DD,well EN EN CMOS logic gates BL[N-1] GND ,well GND BL[N-1] + - - inA[N-1] inB[N-1] + WL[N] WL[N] WL[N-1] WL[N-1] EN EN GND ,well GND GND GND ,well GND ,well MUX1 MUX0 GND 15
Physical Location of RRAMs ▲ Close to input inverters or output inverters? Well spacing: L (a) MET2 VIA VIA RRAM VIA MET1 WL[N] WL[0] CON BL[N] BL[0] CON CON in[0] V DD,well GND well V DD V prog out V DD in[0] GND GND TACT TACT TACT N+ N+ N+ P+ P+ N+ P++ P++ N+ P+ P+ N++ P+ P+ N+ P++ N++ N+ P+ P+ N+ N+ P++ N-Well P-Well P-Well Deep N-Well Well spacing: L MET2 (b) y x VIA RRAM MET1 MET1 in[0] WL[0] BL[0] BL[N] WL[N] CON GND well CON in[0] CON V DD,well V DD,well GND V DD GND out TACT TACT TACT N+ N+ P++ N+ P+ P+ P+ P+ N+ P++ N++ P+ P+ N+ P+ P+ N++ N++ N+ N+ P++ N+ N-Well P-Well Deep N-Well P-Well 16
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