Photon Detector Electronics: Ganging Scenarios Zelimir Djurcic, - PowerPoint PPT Presentation

Photon Detector Electronics: Ganging Scenarios Zelimir Djurcic, Patrick De Lurgio, Gary Drake, Michael Oberling Argonne National Laboratory DUNE Photon Detection Workshop, May 17-18 2016

SiPM Ganging Scenarios • Several Ganging scenarios have been suggested • Motivation: Reduce channel cost • Besides cost, there are other aspects of system design that can impact the deployment and operation of a system, including: electronics performance, complexity, risk, and reliability • Cost also has two aspects: development cost (engineering) and production, which often play off against each other. • This talk is an attempt to analyze the scenarios in a relative way • The scenarios considered are: • Baseline Design: Gang 3 SiPMs together passively on the SiPM board • Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SSP board and add an intermediate active summer, possibly at the warm interface • Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP • Alternative Design #4: Cold Summing Circuits • Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the cable plant, and change the SSP for lower performance, higher channel count 2

SiPM Ganging Scenarios • Baseline Design: Gang 3 SiPMs together passively on the SiPM board HV ADC Power Each ch ADC (12) Readout Channels Per Module ADC SSP Power ADC 4 Groups 3 SiPMs CAT6a Cable Existing SSP Electronics Each 4 Shielded Twisted Pairs With New connectors 3

SiPM Ganging Scenarios (Cont.) • Baseline Design: Gang 3 SiPMs together passively on the SiPM board (Cont.) • Simple system design • Avoids intermediate infrastructure • Reduces cable plant & connectors • Handles signals on cables properly • Efficient in biasing SiPMs from the SSP • Provides good capability for diagnostics  Charge Injection • Requires modest change to SSP for the new connectors • Reduces channel cost by X3 of current (already in the cost est.)  Bottom line: We think that we can • Degrades S/N by 30%, & increases make this work, but it is at the decay by a factor of ~X2 performance limit • Large capacitance of the source may  R&D: Minimal, with limited need impedance compensation at changes to SSP for the new cable source plant, ~ a few weeks of engineering • Does not allow for other cost-saving  Production cost: Moderate, without measures (SSP redesign) further improvements to SSP • Increased single point failures 4

SiPM Ganging Scenarios (Cont.) • Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SiPM board and add an intermediate active summer, possibly at the warm interface HV Power HV Power Each ch Each ch ? ? ADC Summer SSP Module Power Power 4 Groups Existing SSP Electronics 3 SiPMs CAT6a Cable New Intermediate Per 4 Shielded With New connectors? Summer Module Group Twisted Pairs 5

SiPM Ganging Scenarios (Cont.) • Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SiPM board and add an intermediate active summer (Cont.) • Requires modest change to SSP for the new connectors • Have 2 cable termination problems • Complex system design • Must have intermediate infrastructure • Increases cable plant & connectors • Inefficient in biasing SiPMs from the SSP • Poor capability for diagnostics • Requires development costs (Comparison to original cost-saving  Bottom line: Poor from a system R&D?...) perspective, modest R&D, significant worries • Additional signal processing will add about performance noise, and reduce precious S/N headroom  R&D: Development of high-performance further • Circuits amplify & sum noise from cable Summing Module, new cable plant, minimal • Summing circuits are hard to implement changes to SSP without losing bandwidth ~5 man-months of engineering • Significant increase of single point  Production cost: SSPs read out 144 ch failures SiPMs, but have cost of Summing Modules 6

SiPM Ganging Scenarios (Cont.) • Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP HV Power Each ch ADC (12) Readout Channels Per Module SSP Power 4 Groups 3 SiPMs New SSP Electronics CAT6a Cable Per 4 Shielded Twisted Pairs With New connectors Group 7

SiPM Ganging Scenarios (Cont.) • Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP (Cont.) • Simple system design • Avoids intermediate infrastructure • Reduces cable plant & connectors • Handles signals on cables properly • Efficient in biasing SiPMs from the SSP • Provides good capability for diagnostics  Charge Injection • Requires SSP redesign to add summing circuits  Development costs (Compare to original cost-saving  Bottom line: Good from a system R&D?...) perspective, modest R&D, but worries • Additional signal processing will add noise, and reduce precious S/N headroom about performance  R&D: Development of high- further • Circuits amplify & sum noise from cable performance Summing Circuits for the • Summing circuits are hard to implement SSP, new cable plant without losing bandwidth ~3 man-months of engineering • Modest increase in single point failures  Production cost: SSPs read out 144 ch SiPMs, but have more circuitry 8

SiPM Ganging Scenarios (Cont.) • Alternative Design #4 – Cold Summing Circuits Summer Power HV ADC Power Each ch (12) Readout Channels ADC Sum N Per Module SSP ADC Power CAT6a Cable Existing SSP Electronics Matched Individual SiPMs,12 per Module 4 Shielded With New connectors Summed into M Circuits Twisted Pairs 9

SiPM Ganging Scenarios (Cont.) • Alternative Design #4 – Cold Summing Circuits (Cont.) • Moderate system design • Moderate intermediate infrastructure • Good cable plant & connectors • Handles signals on cables properly • Biasing SiPMs could be done from the SSP • Requires modest change to SSP for the new connectors • Best way to handle SiPM signal processing – amplifier close, no cable • Good noise performance- Amplify signal before driving onto the cable • Requires external power supply for the  Bottom line: Good from a system cold electronics perspective, modest R&D, should have • May require other control signals? good performance • Requires mech support on the detector  R&D: New cable plant + cold, high- • Reduced capability for diagnostics performance Summing Circuits, • Requires development costs ~4 man-months of engineering (But already started at IU...)  Production cost: SSPs read out • Summing circuits are hard to implement 144 SiPMs, but have cold electronics without losing bandwidth • Significant risk of single point failures 10

SiPM Ganging Scenarios • Original proposal – SSP Redesign: Gang 3 SiPMs together passively, change the cable plant, and change the SSP for lower performance, higher channel count HV Power Each ch Commercial ASIC (64) Readout Channels Per Module SSP Power 4 Groups 3 SiPMs CAT6a Cable Existing SSP Electronics Each 4 Shielded Twisted Pairs With New connectors 11

SiPM Ganging Scenarios (Cont.) • Original proposal – SSP Redesign: Gang 3 SiPMs together passively, new cable plant, modify SSP for lower performance, higher channel count (Cont.) • Simple system design • Avoids intermediate infrastructure • Minimizes cable plant & connectors • Handles signals on cables properly • Efficient in biasing SiPMs from the SSP • Provides good capability for diagnostics  Charge Injection • Reduces channel cost by ~X15 of current • More closely resembles what might be needed for DUNE  Bottom line: This would be the most • Requires significant change to SSP appropriate path for DUNE • Requires some R&D  R&D: Major changes to SSP • Degrades S/N by 30%, & increases ~ 6 months of engineering decay by a factor of ~X2  Production cost: SSPs read out • Large capacitance of the source may 192 SiPMs need impedance compensation at source 12

Summary • How to navigate the complex parameter space? System attributes considered: • Performance Benefits • System Complexity • Risk • R&D requirements • Production Costs Disclaimer: The following are my personal opinions as to the relative ranking of the different scenarios for these attributes. You are free to challenge them or rank them yourselves… It is meant to be provocative, but also point out the different issues with deciding on an architecture… 13

Summary I • 5 Scenarios, grouped by Performance Benefits 1. Alternative Design #4 – Cold Summing Circuits Best Performance 2. Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the cable plant, and change the SSP for lower performance, higher channel count 3. Baseline Design : Gang 3 SiPMs together passively on the SiPM board 4. Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP 5. Alternative Design #2 – Summer Module: Gang 3 SiPMs Least together passively on the SiPM board and add an Performance intermediate active summer, possibly at the warm interface 14