Partitioning ECE6133 Physical Design Automation of VLSI Systems Prof. Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology
Partitioning P artitioning System design Decomposition of a complex system into smaller subsystems. Each subsystem can be designed independently speeding up the design process. Decomposition scheme has to minimize the interconnections between the subsystems. Decomposition is carried out hierarchically until each subsystem is of managable size. Module 1 Module 2 Module 3 Module n Interface Information ��� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning P artitionin g of A Circuit Input size � �� (a) � (b) Cut � � � Cut � � � Size � � �� Size � � �� Size � � �� ��� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning P artitioning at di�eren t lev els Partitioning System Board Chip Level Level Level System Board System Level Board Board Board Chip Level Level Level Chip Chip Chip Level Level Level ��� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning Problem F orm ulation �� In terconnections b et w een partitions� k k Obj � � i � � � is minimized c � j X X ij � i �� �� j �� Dela y due to partitioning� Obj � max � H � p �� is minimized i � p � P i �� Num b er of terminals� � Cons � ount � V � � C � T � � i � k � i i where� is the cutsize b et w een partitions and � c V V ij i j � p � is the n um b er of times a h yp erpath is cut� H p i i ount � V � is the terminal coun t for partition � C V i i ��� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning Problem F orm ulation �� Area of eac h partition� min max Cons � A � Ar ea � V � � A � i � � � � � � � � � k � i i i �� Num b er of partitions� � Cons � K � k � K � min max The partitioning problem at an y lev el or design st yle deals with one or more of the ab o v e parameters� ��� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning Methods • Top-down Partitioning (cutsize only) – Iterative improvement [KL70, FM82, Kr84, San89] – Spectral based [HK92, AZ95] – Clustering method [SU72, NOP87, WC92, SS93, CS93, HK95] – Network flow based [YW94, YW97] – Analytical based [RDJ94, LLC95] – Multi-level [CS93, HB95, AHK97, KA+97, KK99] • Bottom-up Clustering (delay only) – Unit delay model [LLT69, CD93] – General delay model [MBV91, RW93, YW95] – Sequential circuits with retiming [PKL98, CLW99, CL00]
Partitioning Kernighan�Lin Algorithm � It is a bisectioning algorithm The input graph is partitioned in to t w o subsets of equal sizes� � Till the cutsize k eeps impro ving� � V ertex pairs whic h giv e the largest decrease in cutsize � � are exc hanged These v ertices are then lo c k ed � If no impro v emen t is p ossible and some v ertices are still � unlo c k ed� the v ertices whic h giv e the smallest increase are exc hanged � W� Kernighan and S� Lin� Bell System T ec hnical Journal� ����� ���� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning Kernighan�Lin Algorithm KL Algorithm b egin INITIALIZE��� while � IMPR O VE� tabl e � � TR UE � do �� if an impro v emen t has b een made during last iteration� the pro cess is carried out again� �� � UNLOCK� A � � TR UE � while do �� if there exists an y unlo c k ed v ertex in A � more ten tativ e exc hanges are carried out� �� � eac h � for a A do � if � a � unlo cke d � then for � eac h b B � do � � if � b � unlo cke d � then if � D � D � a � � D � b �� then max D � D � a � � D � b �� max � a � a max � b � b max TENT�EX CHGE� a �� � b max max LOCK� a �� � b max max LOG� tabl e �� � �� � D max A CTUAL�EX CHGE� tabl e �� end� ���� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Kernighan-Lin Algorithm � Perform single KL pass on the following circuit: � KL needs undirected graph (clique-based weighting) Practical Problems in VLSI Physical Design KL Partitioning (1/6)
First Swap Practical Problems in VLSI Physical Design KL Partitioning (2/6)
Second Swap Practical Problems in VLSI Physical Design KL Partitioning (3/6)
Third Swap Practical Problems in VLSI Physical Design KL Partitioning (4/6)
Fourth Swap � Last swap does not require gain computation Practical Problems in VLSI Physical Design KL Partitioning (5/6)
Summary � Cutsize reduced from 5 to 3 � Two best solutions found (solutions are always area-balanced) Practical Problems in VLSI Physical Design KL Partitioning (6/6)
Partitioning Dra wbac ks of K�L Algorithm � K�L algorithm considers balanced partitions only � As v ertices ha v e unit w eigh ts� it is not p ossible to � allo cate a v ertex to a partition� � The K�L algorithm considers edges instead of h yp eredges� � � High� � n � complexit y � � O ���� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning Fiduccia�Mattheyses Algorithm This algorithm is a mo di�ed v ersion of Kernighan�Lin Algorithm� A single v ertex is mo v ed across the cut in a single mo v e whic h � p ermits handling of un balanced partitions� The concept of cutsize is extended to h yp ergraphs� � V ertices to b e mo v ed are selected in a w a y to impro v e � � time complexit y � A sp ecial data structure is used to do this� � � � Ov erall time complexit y of the algorithm is � n �� O C� M� Fiduccia and R� M� Mattheyses� ��th D A C� ����� ���� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Partitioning Data Structure Used in Fiduccia�Mattheyses Algorithm +pmax Ist Partition Vertex # Vertex # -pmax Vertex List of free . . . . . . . . . n 1 2 vertices +pmax IInd Partition Vertex # Vertex # -pmax Vertex . . . . . . . . . n 1 2 ���� j c Sherw ani �� A lgorithms for VLSI Physic al Design A utomation
Fiduccia-Mattheyses Algorithm � Perform FM algorithm on the following circuit: � Area constraint = [3,5] � Break ties in alphabetical order. Practical Problems in VLSI Physical Design FM Partitioning (1/12)
Initial Partitioning � Random initial partitioning is given. Practical Problems in VLSI Physical Design FM Partitioning (2/12)
Gain Computation and Bucket Set Up Practical Problems in VLSI Physical Design FM Partitioning (3/12)
First Move Practical Problems in VLSI Physical Design FM Partitioning (4/12)
Second Move Practical Problems in VLSI Physical Design FM Partitioning (5/12)
Third Move Practical Problems in VLSI Physical Design FM Partitioning (6/12)
Forth Move Practical Problems in VLSI Physical Design FM Partitioning (7/12)
Fifth Move Practical Problems in VLSI Physical Design FM Partitioning (8/12)
Sixth Move Practical Problems in VLSI Physical Design FM Partitioning (9/12)
Seventh Move Practical Problems in VLSI Physical Design FM Partitioning (10/12)
Last Move Practical Problems in VLSI Physical Design FM Partitioning (11/12)
Summary � Found three best solutions. � Cutsize reduced from 6 to 3. � Solutions after move 2 and 4 are better balanced. Practical Problems in VLSI Physical Design FM Partitioning (12/12)
Probing Further � FM Algorithm � [Krishnamurthy, 1984]: developed “look-ahead” gain concept, where gain is now a vector. � [Sanchis, 1989]: perform “flat” multi-way partitioning, where gain considers all possible destinations � [Cong and Lim, 1998]: showed that recursive is way better than flat multi-way partitioning, improved flat method � [Dutt and Deng, 1996]: encourages neighboring cell move, effective in avoiding cutting clusters � [Hagen et al, 1997]: showed that LIFO bucket works better than FIFO � [Hauck and Borriello, 1997]: evaluated all existing FM extensions and proposed the “best” combination Practical Problems in VLSI Physical Design
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