Part II: Timing Closure Today Lou Scheffer Lou Scheffer Cadence - PowerPoint PPT Presentation

Part II: Timing Closure Today Lou Scheffer Lou Scheffer Cadence Cadence San Jose, CA San Jose, CA Lou@cadence.com Lou@cadence.com ASP-DAC'01 Lou Scheffer 1

Timing Closure Today Design Entry • Timing more accurate as flow progresses • Sometimes an earlier stage thinks timing is Synthesis OK, but it fails a later stage Timing • Need to repeat one or more steps with tighter constraints Place • We have a timing closure problem when this process fails. Symptoms include: Timing • Non-convergence Route • Too many iterations • Solution achievable, but this flow Timing cannot find it. ASP-DAC'01 Lou Scheffer 2

The Timing Closure Problem Performance of Circuit Test 7 100 100 99 99 96 Frequency (Target !00MHz) 95 90 pks regular 85 83 80 78 75 PKS/WLM P&R IPO P&R Stage ASP-DAC'01 Lou Scheffer II-3

Examples of Problems Worst slack / # misses Worst slack / # misses Cycle Cycle Design Tech Design Tech time time Synthesis Placed Synthesis Placed C1 -1 / 2000 1 / 2000 -12 / 38k 12 / 38k 7.5 ns .25 µ µ m m C1 - - 7.5 ns .25 V1 V1 0 / 0 0 / 0 -12 / 15k - 12 / 15k 7.5 ns 7.5 ns .18 µ .18 µ m m T1 -0.5 / 2000 0.5 / 2000 -48 / 164k 48 / 164k 2.5- -10 ns 10 ns .18 µ µ m m T1 - - 2.5 .18 P1 -0.4 / 100 0.4 / 100 -97 / 43k 97 / 43k 8 ns .25 µ µ m m P1 - - 8 ns .25 V2 -0.5 / 500 0.5 / 500 -11 / 2000 11 / 2000 7.5 ns .18 µ µ m m V2 - - 7.5 ns .18 ASP-DAC'01 Lou Scheffer 4

Agenda I Traditional design flows Traditional design flows I I Summary of DSM Problems Summary of DSM Problems I I Timing Analysis Overview Timing Analysis Overview I I Timing Correction Overview Timing Correction Overview I I Approaches to Fixing Timing Closure Approaches to Fixing Timing Closure I I Experimental Results Experimental Results I I Summary Summary I ASP-DAC'01 Lou Scheffer II-5

Traditional Design Flows 1. Tech independent Design Entry optimization Synthesis 2. Tech mapping 3. Rudimentary Timing timing correction Place Timing Route Timing ASP-DAC'01 Lou Scheffer II-6

Logic Synthesis Flow I Technology independent optimization Technology independent optimization I N General goal: reduce connections, literals, General goal: reduce connections, literals, N redundancies, area redundancies, area I Technology mapping Technology mapping I N Map logic into technology library Map logic into technology library N I Timing correction Timing correction I N Find and fix critical timing paths Find and fix critical timing paths N N Fix electrical violations (load, slew) Fix electrical violations (load, slew) N ASP-DAC'01 Lou Scheffer II-7

Traditional Design Flows Design Entry 1. Tech independent optimization Synthesis 2. Tech mapping w/Timing 3. Timing correction Place w/Timing Route Timing Integrate timing with synthesis and placement ASP-DAC'01 Lou Scheffer II-8

Agenda I Traditional design flows Traditional design flows I I Summary of DSM Problems Summary of DSM Problems I I Analysis Methods Overview Analysis Methods Overview I I Correction Methods Overview Correction Methods Overview I I Approaches to Fixing Timing Closure Approaches to Fixing Timing Closure I I Experimental Results Experimental Results I I Summary Summary I ASP-DAC'01 Lou Scheffer II-9

The Wall I Logic designers concentrate on logic and Logic designers concentrate on logic and I timing (as understood by synthesis) timing (as understood by synthesis) I Design work done in abstract world of gates Design work done in abstract world of gates I and wire load models and wire load models I Throw design Throw design over the wall over the wall when complete when complete I I Physical designers concentrate on layout Physical designers concentrate on layout I and ability to route and ability to route I Effective method for many years Effective method for many years I ASP-DAC'01 Lou Scheffer II-10

General CMOS Problems I Low drive strengths / low power Low drive strengths / low power I N Capacitance (not intrinsic delay) plays a large Capacitance (not intrinsic delay) plays a large N role in performance role in performance N Variability Variability – – range between slowest possible range between slowest possible N and fastest possible and fastest possible I Noise affects delay Noise affects delay I N IR drop a big percentage of supply IR drop a big percentage of supply N N Crosstalk Crosstalk can change delay by a factor of 2 can change delay by a factor of 2 N ASP-DAC'01 Lou Scheffer II-11

Additional DSM Problems I High density / huge designs High density / huge designs I I Very thin and resistive wires Very thin and resistive wires I I Very high frequencies Very high frequencies I N Inductance becomes more important Inductance becomes more important N I Smaller voltages Smaller voltages I N IR drop a bigger fraction of signal swing IR drop a bigger fraction of signal swing N I Clock skew and latency Clock skew and latency I I Electromigration and noise Electromigration and noise I ASP-DAC'01 Lou Scheffer II-12

Clock Distribution Problems I Most common design approach requires Most common design approach requires I close to zero skew close to zero skew I CMOS / DSM problems all affect clocks CMOS / DSM problems all affect clocks I I Distribution problem increasing Distribution problem increasing I N Number of latches/flip Number of latches/flip- -flops growing flops growing N significantly significantly I Power consumed in clock tree significant Power consumed in clock tree significant I N ∆ ∆ I I and noise also of concern and noise also of concern N ASP-DAC'01 Lou Scheffer II-13

Process Designers are trying to help I Many metal layers Many metal layers I I Different metal pitches Different metal pitches I N Small pitch for local interconnect Small pitch for local interconnect N N Big pitch for long, fast wires Big pitch for long, fast wires N I Copper wires, thick metal to lower R Copper wires, thick metal to lower R I I SOI SOI – – Silicon On Insulator Silicon On Insulator I I Low k dielectrics Low k dielectrics I I These help but are not enough These help but are not enough I ASP-DAC'01 Lou Scheffer II-14

Agenda I Traditional design flows Traditional design flows I I Summary of DSM Problems Summary of DSM Problems I I Analysis Methods Overview Analysis Methods Overview I I Correction Methods Overview Correction Methods Overview I I Approaches to Fixing Timing Closure Approaches to Fixing Timing Closure I I Experimental Results Experimental Results I I Summary Summary I ASP-DAC'01 Lou Scheffer II-15

Timing Analysis I Give accurate time values on each pin/port Give accurate time values on each pin/port I of the network of the network I Has to deal with design changes in Has to deal with design changes in I optimization toolbox optimization toolbox I Static Static Timing Analysis Timing Analysis I N Simulation far too slow in optimization Simulation far too slow in optimization N environment environment N Accuracy is more than enough Accuracy is more than enough N ASP-DAC'01 Lou Scheffer II-16

Timing Analysis Requirements I Choose combination of timing analyzer and delay Choose combination of timing analyzer and delay I calculator which are appropriate for level of calculator which are appropriate for level of design design N give the best accuracy give the best accuracy N N for performance that can be tolerated for performance that can be tolerated N I Timing Analysis / Delay calculation must be able Timing Analysis / Delay calculation must be able I to cope with logic design changes to cope with logic design changes N Incremental Incremental N N Highest performance possible Highest performance possible N N Non Non- -linear delay equations linear delay equations N ASP-DAC'01 Lou Scheffer II-17

Timing Analysis Requirements I Must handle… Must handle… I N Difference between rising and falling delays Difference between rising and falling delays N N Delay dependent on slew rate Delay dependent on slew rate N N Slew and delay dependent on output load Slew and delay dependent on output load N N Non Non- -linear delay equations linear delay equations N ASP-DAC'01 Lou Scheffer II-18

Late Mode Analysis Definitions d ax a AT RAT y a x x AT b b c � Constraints: assertions at the boundaries Constraints: assertions at the boundaries � – Arrival times: Arrival times: AT AT a , AT AT b – a , b – Required arrival time: – Required arrival time: RAT RAT x x � Delay from Delay from a a to to x x is the longest time it takes to is the longest time it takes to � propagate a signal from a a to to x x propagate a signal from � Slack is required arrival time Slack is required arrival time - - arrival time. arrival time. � ASP-DAC'01 Lou Scheffer II-19

Example = − = − SL 1 2 1 = − = y SL 0 0 0 a = AT 2 = a y = AT 0 RAT 2 y a x 1 = x AT 1 1 b b = c AT 3 = x AT 0 = − = − SL 0 1 1 c = − = − b SL 2 3 1 = − = x SL 1 0 1 c ASP-DAC'01 Lou Scheffer II-20