PAM : A P rocessor A geing M odel Based on Critical Path Delays Negar - PowerPoint PPT Presentation

PAM : A P rocessor A geing M odel Based on Critical Path Delays Negar Miralaei, Jyothish Soman, Timothy Jones March 2014 Designing with Uncertainty - Opportunities & Challenges Workshop

Agenda • Ageing model to Application characterise the applications’ behaviour Ageing Ageing • Micro-Architectural Model Prevention model • Runtime based ageing Multicore/ prevention schemes Many-core 2

Transistor Ageing • Major Failure Mechanisms Gate Source(S) Drain(D) Oxide p/n-well (p/n) 3

Transistor Ageing 4

The Gaps in Knowledge • Single core vs multicore and many-core • Memory and cache vs processor • All the units within the processor • The level of implementation 5

Critical Path Delay Estimation • An ageing model based on critical path delay variations 6

Critical Path Delay Estimation Logic Memory (Full Adder) (SRAM cell) Delay of FO4 7

PAM: a Processor Ageing Model • Process variation parameters Calculate • Floorplan file the access • Frequency • Source voltage time • Temperature Failure Mechanisms: Gem5 NBTI & HCI Calculate the switching delay for each structural unit 8

Simulation Environment • Technology parameters • Gem5 Simulator • Process technology = 32nm • SPECCPU 2000 Benchmarks • V dd = 1.0 V • VARIUS Framework • Frequency = 2.0 GHz • Single out of Order ARM v7 core • Ageing Parameters • Temperature = 80 o C • V th0 = 200mV • Oxide thickness = 0.65 nm • Effective gate length = 17nm 9

Results Different structural units delays for one benchmark, ran for 1 billion instructions Delay (ps) Structural Units 10

Results Architectural Registers delay within Renaming Unit for all SPEC2000 benchmarks, ran for 1 billion instructions 11

Results Comparison of the maximum critical path delays for 10 different initial variations, ran for SPEC2000 benchmarks and for 1 billion instructions 12

Summary • Micro-Architectural ageing Application model • Online mechanism giving state of processor’s age Ageing PAM Prevention • Characterising the ageing due to applications’ behaviour Multicore/ Many-core 13

Future Work • Transistor level model • Add more failure mechanisms (EM, TDDB, RTN, etc.) • Combat processor ageing • Compiler techniques (JIT environment) • Scheduling • DVFS • Code restructuring and algorithm selection • Create a heterogeneous CMP with “hot spares” 14

Thank you Questions Please? negar.miralaei@cl.cam.ac.uk http://www.cl.cam.ac.uk/~nm537/ Project webpage: http://www.cl.cam.ac.uk/research/comparch/research/dome.html