10/16/2014 Overview • Motivation and introduction • Model and fault model ECE 553: TESTING AND • Theory TESTABLE DESIGN OF • Checking experiment design g p g DIGITAL SYSTES DIGITAL SYSTES • Limitations of the method • Summary Sequential circuit testing - Checking experiment approach 10/16/2014 2 Motivation and Introduction An example • Consider testing a 4-bit ALU • Ref: F.C. Hennie “Fault detection – We need not know the structure – we can determine the experiments for sequential circuits”, 5 th number of inputs and outputs. If the number is small we annual symposium on switching and can test the circuit exhaustively. automata theory 1964 automata theory, 1964. – Can such a technique be used for sequential circuits, – Can such a technique be used for sequential circuits even if it is fairly small, such as a small finite state • Motivation machine. Such FSMs exist often in practice (embedded controllers are good examples of such FSMs). – Test generation at higher level of abstraction in • Derivation of tests for such circuits is of interest for the which only the function of the circuit is known following two reasons – Need not worry about the realization and underlying technology but the implementation (structure) is not known – Such tests can also be used for validation and verification 10/16/2014 3 10/16/2014 4 Fault model Sequential circuit model • Two ways to express a state machine • Two formulations of the test problem – State table – Given the behavior of the circuit (such as state table), verify the behavior by applying the inputs and – State diagram observing the outputs. Objective is to find a sequence – M = (Q, I, O, NS, OU) M = (Q I O NS OU) of inputs that will verify the behavior Q = set of states – Given a sequence of inputs and outputs, construct a I = set of inputs from an input alphabet state machine that will behave as specified by the input/output sequence O = set of outputs from an output alphabet • The above two problems have similarities but we NS = next state function will address the first of the two problems OU = output function 10/16/2014 5 10/16/2014 6 1
10/16/2014 Fault model Theory • Strongly connected machine/circuit: every state • Assumptions about the faults is reachable from every other state – Number of states in the FSM are known or – There are no “source” or “sink” states these are upperbounded • An example FSM – strongly connected? – No fault causes an increase in the number of No fault causes an increase in the number of states or increase beyond the upperbound PS x = 0 x = 1 • We will also limit our discussion to a class A C/0 A/0 of FSMs that have some special properties. B B/1 D/0 These properties are defined in the “theory” C A/0 B/0 section of the discussion D B/1 C/0 10/16/2014 7 10/16/2014 8 Theory (contd.) Theory (contd.) • Synchronizing tree • Synchronizing sequence PS x = 0 x = 1 PS x = 0 x = 1 • Ambiguity – states the Application of this A C/0 A/0 A C/0 A/0 circuit may be in sequence takes the B B/1 D/0 B B/1 D/0 machine to a known • Example: Example: state (final state), irrespective of C A/0 B/0 - initial ambiguity (ABCD) C A/0 B/0 the start state (initial state) - after an application of 0 D B/1 C/0 D B/1 C/0 of the circuit the ambiguity is (ABC) • Synchronizing tree – see next slide • SS = 0 1 0 1 0 (Final state = B) 10/16/2014 9 10/16/2014 10 Theory (contd.) Theory (contd.) • Homing sequence Construct a homing tree • Homing sequence – application of this sequence PS x = 0 x = 1 010 is a homing sequence and observation of outputs can determine the A C/0 A/0 If output 000 – final state is C final state of the circuit If output 101 – final state is B B B/1 D/0 • Distinguishing sequence – application of this • Distinguishing sequence – C A/0 B/0 sequence and the observation of outputs and Construct a distinguishing tree D B/1 C/0 determine the initial (start) state of the circuit This machine does not have a DS • Transfer sequence – – Clearly this can also determine the final state of the circuit a sequence, Tij, that will take the machine from state i to j 10/16/2014 11 10/16/2014 12 2
10/16/2014 Theory (contd.) Checking experiment design • Example: • Three part sequence PS x = 0 x = 1 • SS ? – Part I: Initialize the FSM to a known state • HS ? A C/0 D/1 – Part 1: verify that the FSM has n states • DS = 100 • DS 100 B C/0 A/1 • Check that there are n distinct states st output st – Part 2: verify that all transitions from every state are C A/1 B/0 A 1 0 0 C correct D B/0 C/1 B 1 0 1 A • Apply one input at a time and check the output and the C 0 0 1 A state of the circuit D 1 1 0 C 10/16/2014 13 10/16/2014 14 Checking experiment design (contd.) Checking experiment design (contd.) • An example PS x = 0 x = 1 • SS = 01010 A C/0 D/1 • Checking sequence construction • DS = 100 • A (DS) -> C B C/0 A/1 – Apply SS and take the circuit to a known state • B (DS) -> A – Repeat for each state • C (DS) -> A C A/1 B/0 • D (DS) -> C ( (known state) DS (transfer to another, different, state) ) ( , , ) D D B/0 B/0 C/1 C/1 DS is used to verify the known state • Phase 1: SS T CA DS T CB DS T AC DS T AD DS – Repeat of each state and every input C C A A C (known state) input DS (transfer to a known state) verify output when input is applied • Phase 2: T CA 0 DS T AA 1 DS … DS is used to verify that the transition was indeed correct check null check output output 10/16/2014 15 10/16/2014 16 Limitations of the method Checking experiment design (contd.) • Assumptions are very restrictive and limit the application of the method • Checking sequence – reducing sequence length • Machine do not have SS, DS, etc. require more – States need not be verified in the order we want complex algorithms them, they can be verified as they appear while • Length of the sequence can be very long designing the sequence designing the sequence – SS can be as long as O(n 3 ) – Phases 1 and 2 can be overlapped • The known best bound is n(n+1)(n-1)/6 – TS can be no longer than length n – Overlap parts of sequences where ever possible – DS – this can be very long in theory – If there is more than one DS, these can be integrated • (n-1)n n with in the design of sequence – Hence total sequence length can be O(2 kn ), where k is the number of flip-flops and n=2 k 10/16/2014 17 10/16/2014 18 3
10/16/2014 Summary • Need for functional testing methods for sequential circuits • Described a fault model for functional faults in FSMs FSMs • Developed theoretical foundation for FSM testing • Design of test sequence • Limitations of the method 10/16/2014 19 4
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