Outline The Esterel Language Introduction to Esterel and Existing - PowerPoint PPT Presentation

Outline The Esterel Language Introduction to Esterel and Existing Compilers Developed by G´ erard Berry starting 1983 My Software Compiler [DAC 2000, TransCAD 2002] Originally for robotics applications Compiling Esterel My Hardware Compiler [SLAP 2002, IWLS 2002] Imperative, textual language Stephen A. Edwards Synchronous model of time like that in digital circuits Department of Computer Science, Concurrent Columbia University www.cs.columbia.edu/˜sedwards sedwards@cs.columbia.edu An Example An Example An Example Wait for next cycle where A is present loop Infinite Loop Force signal present in this cycle await A; await A; emit B; emit B; emit B; present C then Make D present if C is present C then present C then emit D end; emit D end; emit D end; pause pause end Wait for next cycle An Example An Example An Example every R do every R do loop loop loop Restart on R await A; await A; await A; emit B; emit B; emit B; present C then present C then present C then emit D end; emit D end; emit D end; pause pause pause end end end || Run Concurrently || || Same-cycle bidirectional communication loop loop loop present B then present B then present B then emit C end; emit C end; emit C end; pause pause pause end end end end end

An Example Automata Compilers Netlist-based Compilers every R do Esterel is a finite-state language, so build an automata: A = entry || s2q; entry loop cf = !C && s1q; await A; switch (s) { loop s1d = cf || A; emit B; A emit A; await C; case 0: A = 1; s = 1; break; present C then B = s2d = C && s1q; loop case 1: if (C) { B = 1; s = 0; } break; emit B; pause Good for hierarchical FSMs emit D end; emit A; await C; } pause end Clean semantics, emit B; pause Bad at manipulating data end scales well, but || end V1, V2, V3 (INRIA/CMA) [Berry, Gonthier 1992] inefficient. Hardware Esterel variant C loop proposed to address this present B then Fastest known code; great for programs with few states. Can be 100 times emit C end; B slower than automata Does not scale; concurrency causes state explosion. pause end code. end Discrete-Event Based Compilers Overview SAXO-RT [Weil et al. 2000] Divides Esterel program into if ((s0 & 3) == 1) { if (S) { every R do R event functions dispatched by a fixed scheduler. R loop s3 = 1; s2 = 1; s1 = 1; await A; s 1 2 emit B; } else unsigned curr = 0x1; A present C then s B if (s1 >> 1) My Esterel Compiler for Software emit D end; 1 2 unsigned next = 0; pause t=0 t=1 s1 = 3; end A || else { B static void f1() { loop B B C if ((s3 & 3) == 1) { Presented at DAC 2000 (also TransCAD 2002) A = 1; present B then C C emit C end; 0 t 1 s3 = 2; t3 = L1; curr &= ˜0x1; next |= 0x2; pause D C end } else { } D Used inside Synopsys’ CoCentric System Studio to end loop s=2 s=1 t3 = L2; s=2 s=1 } static void f2() { generate control code emit A; await C; if (!C) return; Esterel Concurrent Sequential C code B = 1; emit B; pause curr &= ˜0x2; next |= 0x1; Source CFG CFG end } void tick() { if (curr & 0x1) f1(); if (curr & 0x2) f2(); curr |= next; next = 0; } Translate every Add Threads Split at Pauses every R do every R do every R do loop loop loop R R R await A; await A; await A; emit B; emit B; emit B; present C then present C then present C then s emit D end; emit D end; emit D end; 1 2 pause pause pause end end end || || || loop loop loop present B then present B then present B then emit C end; emit C end; emit C end; pause pause pause end end end s=2 s=1 end end end

Add Code Between Pauses Translate Second Thread Finished Translating every R do every R do every R do loop loop loop R R R await A; await A; await A; emit B; emit B; emit B; present C then present C then present C then s s s emit D end; emit D end; emit D end; 1 2 1 2 1 2 pause pause pause A A A end end end || || || B B B B B loop loop loop present B then present B then present B then C C C C C emit C end; emit C end; emit C end; D D D pause pause pause end end end s=2 s=1 s=2 s=1 s=2 s=1 end end end Add Dependencies and Schedule Run First Node Run First Part of Left Thread R R R R every R do loop s 1 2 R await A; A emit B; s s 1 2 1 2 B present C then A A s emit D end; 1 2 pause B B B B A end || C C C C B B loop D D present B then C C emit C end; s=2 s=1 s=2 s=1 D pause end s=2 s=1 end Context Switch Run Right Thread Context Switch R R R R R R s s s 1 2 1 2 1 2 A A A s s s 1 2 1 2 1 2 B B B A A A t=0 t=1 t=0 t=1 t=0 t=1 B B B B B B B B C C C C C C C C D D D t 0 1 s=2 s=1 s=2 s=1 s=2 s=1

Size of Generated Code on an Finish Left Thread Completed Example UltraSparc-II R R R R s s 1 2 1 2 2M A A s s 1 2 1 2 B B A A t=0 t=1 t=0 t=1 256K B B B B B B EventDriven C C C C C C 32K ContextSwitch D D t t 0 1 0 1 OptNetlist s=2 s=1 s=2 s=1 C C Netlist 4K D D Automata s=2 s=1 s=2 s=1 50 100 200 500 1000 2k 5k Nodes Average Cycle Times on an Size of Generated Code on a Average Cycle Times on a Pentium Pentium UltraSparc-II 1ms 256K 100us 100us 10us 32K EventDriven ContextSwitching 10us EventDriven 1us OptNetlist ContextSwitch EventDriven Netlist ContextSwitch OptNetlist 4K 1us 0.1us OptNetlist Automata Netlist Netlist Automata 0.1us Automata 50 100 200 500 1000 2k 5k Nodes 50 100 200 500 1000 2k 5k 50 100 200 500 1000 2k 5k Nodes Nodes Translation to CCFG Translation to PDG S S S every S do await I; s2 s3 s2 s3 weak abort My Esterel Compiler for Hardware s2=1 s3=1 sustain R I I when immediate A; The ESUIF Open Source Esterel Compiler R R emit O s2 s3 R A A || R A A (Work in Progress) s3=2 s2=0 I loop 1 1 2 1 1 2 Presented at SLAP 2002, IWLS 2002 pause; pause; s2=1 R s3=1 present R then A emit A end O s3=1 s3=2 O s3=1 s3=2 end R 1 A s2=0 s2=0 end s2=0 s2=0 s2=1 1 2 s2=1 s2=2 s2=1 s3=1 s2=1 s2=2 s2=1 s3=1 O s2=0

Translation to Circuitry Summary Introduction to Esterel and Existing Compilers Go S Synchronous, Concurrent, Textual Language Thanks For Your Attention S Automata, Netlist, and Control-based compilers Stephen A. Edwards s2=1 s3=1 My Software Compiler [DAC 2000, TransCAD 2002] s2=1 s3=1 Department of Computer Science s2 s3 Translate to Concurrent CFG, schedule, then Columbia University s3=2 s2=0 I synthesize Sequential CFG www.cs.columbia.edu/˜sedwards s3=2 s2=0 s2=1 R s3=1 My Hardware Compiler: ESUIF [SLAP 2002, IWLS 2002] sedwards@cs.columbia.edu I s2=1 s3=1 A R Translate CCFG to Program Dependence Graph A Trivially translate PDG to circuitry R 1 A R 1 A s2=1 Open-source, under development 1 2 1 2 s2=1 O s2=0 O s2=0