Improving Controller Synthesis from Esterel Cristian Soviani Jia - PowerPoint PPT Presentation

Improving Controller Synthesis from Esterel Cristian Soviani Jia Zeng Stephen A. Edwards Department of Computer Science, Columbia University www.cs.columbia.edu/˜{soviani,jia,sedwards} {soviani,jia,sedwards}@cs.columbia.edu

Why controllers ? Several state machines drive the bulk logic (data paths) Small area. Delay is critical. Even a simple “behaviour” leads to infernal RTL Most bugs are here. Verification is critical. > OFF -> BLINKING -> ON Typical applications: button init=1 various device controllers (e.g. Eth. MAC) D Q bus interfaces & arbiters scheduling pipelined units init=1 D Q Is it correct ? ——- led

A delicate compromise to avoid Corectness vs. Performance rst R C C select cs cs2 cs1 xfer_ack D Q D Q D Q addr addr. decoder to data paths from Xilinx, EDK3.1 docs, Designing Custom OPB Slave Peripherals for Microblaze A master who assumed control of the bus may terminate, or abort, the transfer at any time by deasserting select . All slaves are required to terminate the transfer in progress and reset their state machines if the select signal is deactivated ... if the select is deactivated in the cycle in which the slave would have activated xferAck , then the slave must deactivate the xferAck signal in this cycle from IBM, On-Chip Peripheral Bus, Architecture Specifications, v2.1

Simplified OPB SSRAM controller 1 module opb_ram_ctrl: 2 input SEL, RNW, A3, A2, A1, A0; 3 output XFER_ACK; You’ve already seen: 4 output OREG_CE, OREG_RES; - reads require more cycles that writes 5 output MEM_RD, MEM_WR; - deasserting select aborts the opera- 6 loop tion 7 await [ SEL and A3 and ... ]; 8 abort - I included no comments on purpose 9 pause; 10 present RNW then Easy to modify. Try: 11 emit MEM_RD; pause; 12 emit OREG_CE; pause; - removing 8 and 17 13 emit XFER_ACK - removing 9 14 else - adding “pauses” between 11 and 12 15 emit MEM_WR; emit XFER_ACK 16 end 17 when [ not SEL ]; I wrote the sample in 3’ 18 emit OREG_RES; 19 end loop 20 end module

Why Controllers in Esterel ? What language do we want? High level simple to write / modify / understand : powerful sequential and concurrent flavored constructs deterministic : we can’t avoid mathematics high level verification : this is different from simulation EFFICIENT Keep the abstraction near the technology synchronous intuitive translation no “synthesis subset” jokes Esterel is a good candidate

Previsious work. Our Results Esterel technologies : Esterel v5, IC, one-hot enc. D. Potop : GRC, hierarchical enc. Primary target: s/w. H/W synthesis relies on generic seq. optimization (sis/blifopt) CEC : Columbia Esterel Compiler Challenge : use high level info CEC generates corect & efficient circuits To do: improve the circuit delay

Surface & Depth - Termination levels input A, B, C, D; term. level s/d output X, Y, Z; trap T in Surface : hard start trap U, V in present A then pause end # 0 , 1 / 0 Depth : continue || present B then exit T end # 0 , 3 / 0 || Term levels: pause ; 0 : terminated present C then exit U end # 1 / 0 , 2 1 : still running || present D then exit V else 1 , 2 / 0 , 1 2,3 ... exceptions pause ; pause# end handle U do emit X The biggest level wins handle V do emit Y end trap handle T do emit Z end trap

� ✄ ✄ Sample Esterel code module example: input R; Sample timing diagram output A, B, C, D; every R do R �✁� �✁�✂�✁�✁�✁�✂�✁�✁�✁� �✂� loop ✄✁✄ ✄✁✄ emit A; A �✁�✁� pause; emit B; B �✁�✁�✂�✁� �✁� �✁� pause end loop C �✁�✁� �✂�✁�✁�✁�✂�✁�✁�✁�✂� �✁� || emit C; D �✁�✁�✂�✁�✁�✂� �✂�✁�✁�✁�✂�✁�✁�✂�✁� �✁�✁�✂�✁� pause; Note the “strong” priority of “every R” pause; emit D which aborts the curent instructions end every and immediately restarts its body end module

The CFG and ST 0 module example: 0 1 0 input R; 0 1 1 1 1 12 output A, B, C, D; 0 R 2 every R do 0 0 1 2 1 loop 3 4 0 1 emit A; 0 1 3 3 4 4 pause; 5 8 emit B; 0 1 0 1 2 pause 6 7 9 10 11 0 1 end loop 5 8 0 1 || 0 1 1 emit C; A B 0 D 2 A C pause; 7 6 9 10 7 11 pause; 1 0 1 1 1 emit D The Control Flow end every Ghaph (left) and the Selection Tree 1 1 end module (above) 1

☎ Clock 0 : R=0 A=0 B=0 C=0 D=0 0 0 ✝✁✞ ✝✂✞ ✝✂✞✁✝✂✞ 0 1 R 1 0 ☎✆☎ ☎✆☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✟☎ ✝✂✞✂✝✁✞✂✝✂✞✁✝✂✠✆✠✟✞✂✝✁✠✆✠✆✞✁✝✂✠ 1 12 A 1 1 ☎✆☎✆☎ 0 ✝✁✞✂✝✂✞✁✝✂✞ ✝✁✞ ✝✂✞ B 2 ☎✆☎✆☎✟☎✆☎ ☎✟☎ ☎✆☎ R ✝✂✞ ✝✂✞ ✝✁✞✂✝✂✠ C 0 1 0 ☎✆☎✆☎ ☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎✟☎ ☎✆☎ ✝✂✞ ✝✁✞ D 3 4 2 1 ☎✆☎✆☎✟☎✆☎✆☎✟☎ ☎✆☎✆☎✟☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✆☎✟☎✆☎✟☎ every R do 0 1 0 1 3 3 4 4 5 8 loop 0 1 0 1 2 emit A; 6 7 9 10 11 pause; 0 1 emit B; 0 5 8 0 1 0 1 pause 0 1 1 1 12 end loop A B 0 D 2 A C 0 || 2 7 6 9 10 7 11 emit C; 0 1 pause; 1 0 1 1 1 3 4 pause; 0 1 emit D 5 8 1 1 end every 0 1 0 1 2 1 6 7 9 10 11

☎ Clock 1 : R=0 A=0 B=0 C=0 D=0 0 0 ✝✁✞ ✝✂✞ ✝✂✞✁✝✂✞ 0 1 R 1 0 ☎✆☎ ☎✆☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✟☎ ✝✂✞✂✝✁✞✂✝✂✞✁✝✂✠✆✠✟✞✂✝✁✠✆✠✆✞✁✝✂✠ 1 12 A 1 1 ☎✆☎✆☎ 0 ✝✁✞✂✝✂✞✁✝✂✞ ✝✁✞ ✝✂✞ B 2 ☎✆☎✆☎✟☎✆☎ ☎✟☎ ☎✆☎ R ✝✂✞ ✝✂✞ ✝✁✞✂✝✂✠ C 0 1 0 ☎✆☎✆☎ ☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎✟☎ ☎✆☎ ✝✂✞ ✝✁✞ D 3 4 2 1 ☎✆☎✆☎✟☎✆☎✆☎✟☎ ☎✆☎✆☎✟☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✆☎✟☎✆☎✟☎ every R do 0 1 0 1 3 3 4 4 5 8 loop 0 1 0 1 2 emit A; 6 7 9 10 11 pause; 0 1 emit B; 0 5 8 0 1 0 1 pause 0 1 1 1 12 end loop A B 0 D 2 A C 0 || 2 7 6 9 10 7 11 emit C; 0 1 pause; 1 0 1 1 1 3 4 pause; 0 1 emit D 5 8 1 1 end every 0 1 0 1 2 1 6 7 9 10 11

☎ Clock 2 : R=1 A=1 B=0 C=1 D=0 0 0 ✝✁✞ ✝✂✞ ✝✂✞✁✝✂✞ 0 1 R 1 0 ☎✆☎ ☎✆☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✟☎ ✝✂✞✂✝✁✞✂✝✂✞✁✝✂✠✆✠✟✞✂✝✁✠✆✠✆✞✁✝✂✠ 1 12 A 1 1 ☎✆☎✆☎ 0 ✝✁✞✂✝✂✞✁✝✂✞ ✝✁✞ ✝✂✞ B 2 ☎✆☎✆☎✟☎✆☎ ☎✟☎ ☎✆☎ R ✝✂✞ ✝✂✞ ✝✁✞✂✝✂✠ C 0 1 0 ☎✆☎✆☎ ☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎✟☎ ☎✆☎ ✝✂✞ ✝✁✞ D 3 4 2 1 ☎✆☎✆☎✟☎✆☎✆☎✟☎ ☎✆☎✆☎✟☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✆☎✟☎✆☎✟☎ every R do 0 1 0 1 3 3 4 4 loop 5 8 0 1 0 1 2 emit A; 6 7 9 10 11 pause; 0 1 emit B; 0 5 8 0 1 0 1 pause 0 1 1 1 12 end loop A B 0 D 2 A C 0 || 2 7 6 9 10 7 11 emit C ; 0 1 pause; 1 0 1 1 1 3 4 pause; 0 1 emit D 5 8 1 1 end every 0 1 0 1 2 1 6 7 9 10 11

☎ Clock 3 : R=0 A=0 B=1 C=0 D=0 0 0 ✝✁✞ ✝✂✞ ✝✂✞✁✝✂✞ 0 1 R 1 0 ☎✆☎ ☎✆☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✟☎ ✝✂✞✂✝✁✞✂✝✂✞✁✝✂✠✆✠✟✞✂✝✁✠✆✠✆✞✁✝✂✠ 1 12 A 1 1 ☎✆☎✆☎ 0 ✝✁✞✂✝✂✞✁✝✂✞ ✝✁✞ ✝✂✞ B 2 ☎✆☎✆☎✟☎✆☎ ☎✟☎ ☎✆☎ R ✝✂✞ ✝✂✞ ✝✁✞✂✝✂✠ C 0 1 0 ☎✆☎✆☎ ☎✟☎✆☎✆☎✟☎✆☎✆☎✟☎✆☎✟☎ ☎✆☎ ✝✂✞ ✝✁✞ D 3 4 2 1 ☎✆☎✆☎✟☎✆☎✆☎✟☎ ☎✆☎✆☎✟☎✆☎✟☎✆☎✆☎✟☎✆☎ ☎✆☎✟☎✆☎✟☎ every R do 0 1 0 1 3 3 4 4 loop 5 8 0 1 0 1 2 emit A; 6 7 9 10 11 pause; 0 1 emit B; 0 5 8 0 1 pause 0 1 0 1 1 1 12 end loop A B 0 D 2 A C 0 || 2 7 6 9 10 7 11 emit C; 0 1 pause; 1 0 1 1 1 3 4 pause ; 0 1 emit D 5 8 1 1 end every 0 1 0 1 2 1 6 7 9 10 11