Outcomes I can create a state diagram to solve a sequential problem - PowerPoint PPT Presentation

14.1 14.2 Outcomes • I can create a state diagram to solve a sequential problem • I can implement a working state machine given a state diagram Unit 14 State Machine Design 14.3 14.4 Review of State Machines • We've implemented state machines in software, now let's see how we can build them in hardware • State machines are described with state diagrams that show various states, transition arrows between them, and outputs to be generated based on the current state – We use the state to help us know which step of an algorithm we are currently at STATE MACHINES OVERVIEW

14.5 14.6 Hardware State Machines Hardware vs. Software FSM Comparison • Hardware (finite) state machines or (aka FSMs) provide the Hardware FSMs Software FSMs “brains” or control for electronic and electro-mechanical • Changes state (makes a • Changes state (makes a systems transition) every __________ transition) when software polls – Many custom hardware designs use a hardware-based FSM to control the inputs (which could be very • Uses a ___________________ to their operation low frequency) store the current state • FSMs are required to generate output values at specific times • Uses a variable to store the • Designer can choose state 'codes' (i.e. when you need time-dependent hardware outputs) current state arbitrarily but the choice can – Example 1: Traffic light. The system must automatically transition from greatly affect the ______ of the • Programmer can choose state green to yellow to red without any external input stimulus circuit 'codes' arbitrarily with little – Example 2: Sequence detection. Turn an LED on only if a certain code is implication • Uses ___________ (found from a entered over time (e.g. number lock). truth table and K-Map or other • Uses 'if' statements to implement • FSMs require __________ and _____________ logic elements means) to implement the state the state transition arrows – Sequential Logic to remember what step (state) we’re in transition arrows • Must implement the initial value • Encodes everything that has happened in the past • Must implement the initial state of the state variable – Combinational Logic to produce outputs and find what state to go to next value using the ________ signal • Generates outputs based on what state we’re in and the input values 14.7 14.8 Comparison: FSM in SW and HW State Machine Example int main() • Design a sequence detector to check for the combination { unsigned char state=0; // init state "101" unsigned char input, output; while(1) { • Input, X, provides 1-bit per clock _delay_ms(10); // choose appropriate delay input = PIND & (1 << PD0); State Diagram • Check the sequence of X for "101" in successive clocks if(state == 0){ PORTD &= ~(1 << PD7); // output off • If "101" detected, output F=1 (F=0 all other times) if( input ){ state = 1; /* transition */ state=0: Q 1 Q 0 =00 } state=1: Q 1 Q 0 =01 else { state=2: Q 1 Q 0 =10 state = 2; /* transition */ 0 (Next State) (Current State) } (Input) "101" D 0 } PRE X D Q Q 0 else if(state == 1){ X Sequence PORTD &= ~(1 << PD7); // output on Q (Output) F CLR if( input ){ state = 2; } F else { state = 0; } RESET Detector CLK 0 } else if(state == 2) { D 1 Q 1 RESET PRE D Q PORTD |= (1 << PD7); // output on if( !input ) { state = 0; } Q } CLR Hardware } RESET Software Implementation return 0; Implementation } CLK

14.9 14.10 Another State Diagram Example Correct Specification of State Diagrams • “101” Sequence Detector should output F=1 when the • For HW especially, it is critical that exactly __________ sequence 101 is found in consecutive order from a state may be true at a time – We can't go __________ at once and if we don't tell it explicitly where to go next, it may go to any random state – If you want to stay in a state, include an explicit ________ arrow • In SW, the state variable will retain its value, but in HW we must be explicit S101 • On the 2 nd example if you want to stay in Q1, include a loopback labeled Sinit S1 S10 F=0 F=0 F=0 F=1 X=0 State Diagram for “101” Sequence Detector See the end of this slide set for more detailed solutions and explanations. 14.11 14.12 State Machines Correct Specification of State Diagrams 2 • Exactly one transition from a state may be true at a • The HW for a state machines can be broken time into 3 sections of logic – Make sure the conditions you associate with the arrows – State Memory (SM) coming out of a state are _________________ (< 2 true) but all inclusive (> 0 true) • Just FF’s to remember the ________________ – ____________ Logic (NSL) • Combo logic to determine the next state • Essentially implements the transition conditions – ____________ Logic (OFL) • Combo logic to produce the outputs ALWAYS double check your transitions to ensure they are mutually exclusive.

14.13 14.14 State Machine State Machines NEXT STATE • Below is a circuit implementing a state machine, CURRENT STATE The FF inputs will be the value of The FF outputs notice how it breaks into the 3 sections the next state logic output. On represent the current the next clock edge the FF state (the state we’re outputs will change based on in right now) these inputs. (Input) (Next State) (Current State) X D 0 Q 0 OFL D Q (Output) inputs NSL Q F next current Next State Logic State Output outputs state state SM Memory Function D 1 Q 1 Q i D i (Flip- Logic D Q Flops) Q clock CLK Important : State is always represented and stored by the flip-flop outputs in the system 14.15 14.16 State Diagram vs. State Machine State Diagrams State Machine 1. State Memory => Flip Flops (FFs) 1. States n-FF’s => 2 n states – 2. Transition Conditions 2. Next State Logic (NSL) 3. Outputs – combinational logic – logic for FF inputs 3. Output Function Logic (OFL) – MOORE: f(state) State Machines require sequential logic to remember the current state – MEALY: f(state + inputs) (w/ just combo logic we could only look at the current value of X, but now we can take 4 separate STATE MACHINE DESIGN (Input) (Next State) (Current State) actions when X=0) X D 0 Q 0 OFL D Q X=1 On Reset (Output) (power on) X=1 X=0 X=1 NSL Q F Sinit S1 S10 S101 SM F=0 F=0 F=0 F=1 X=0 D 1 Q 1 X=1 D Q X=0 X=0 Q State Diagram for “101” Sequence Detector CLK

14.17 14.18 State Machine Design State Machine Design Coming up with a state diagram is non-trivial • State machine design involves taking a • problem description and coming up with a • Requires creative solutions state diagram and then designing a circuit to Designing the circuit from the state diagram is • implement that operation done according to a simple set of steps • To come up w/ a state diagram to solve a problem – Write out an algorithm or ____________ to solve the Problem Circuit problem State Diagram Description Implementation – Each step in your algorithm will usually be _________ in your state diagram – Ask yourself what past inputs need to be ____________ and that will usually lead to a state representation 14.19 14.20 Consecutive 1 Detector • Given a single-bit input, X, set the output to 1 if the last 2 values of X have been 1 X EXAMPLE 1 Consecutive 1's X F Detector CLK RESET

14.21 14.22 Transition Output Table 6 Steps of State Machine Design 1. State Diagram • Convert state diagram to transition/output table – Show Next State & Output as a function of Current State and Input 2. Transition/Output Table (Q -> Q*) Current Input (X) Next Output 3. State Assignment State State (F) • Determine the # of FF’s required S0 0 On Reset X=1 X=1 • Assign binary codes to replace symbolic names (power on) X=1 S0 1 4. Rename Qi* to Di S0 S1 S2 S1 0 F=0 F=0 F=1 X=0 5. K-Maps for NSL (Di values) and OFL S1 1 X=0 X=0 S2 0 • One K-Map for every FF input S2 1 • One K-Map for every output of OFL 6. Draw out the circuit 14.23 14.24 Transition Output Table Transition Output Table • Now assign binary codes to represent states • Convert state diagram to transition/output table – The order doesn't matter. Use don't cares for unused state codes Next State Current State Output Notice we used Gray Code order. On Reset X = 0 X = 1 X=1 X=1 Current Input Next State Output This will help in a future step (power on) X=1 State State Q 1 Q 0 State Q1* Q0* State Q1* Q0* F S0 S1 S2 F=0 F=0 F=1 Q1 Q0 X Q1* Q0* F X=0 S0 0 0 S0 0 0 S1 1 1 0 X=0 0 0 0 0 0 0 X=0 -- 0 1 -- d d -- d d d 0 0 1 1 1 0 S1 1 1 S0 0 0 S2 1 0 0 0 1 0 State Assignment Mapping S2 1 0 S0 0 0 S2 1 0 1 State Q 1 Q 0 0 1 1 Here we have redrawn the 8 row S0 0 0 On Reset 1 0 0 0 0 1 X=1 X=1 table from the previous slide into (power on) X=1 -- 0 1 4 rows & 2 columns. We've also 1 0 1 1 0 1 S0 S1 S2 separated the output F since it S1 1 1 1 1 0 0 0 0 F=0 F=0 F=1 X=0 doesn't depend on X but only Q1 and Q0 1 1 1 1 0 0 X=0 S2 1 0 X=0