Nanoelectronic Architectures: Reliable Computation on Defective Devices Alex Orailoglu Computer Science & Engineering Department University of California, San Diego La Jolla, CA
Scaling beyond CMO S � Moore’s law – exponential scaling down of transistors � State-of-the-art device: Si based CMOS � Provided several decades of scaling: ~ 45nm currently � Expected to continue for the next several years: – beyond 22nm � Asymptotic end around year 2019: – approaching 6nm � Physical limits of CMOS � Quantum mechanics, fabrication limitations, … � Substantially extending the roadmap beyond CMOS: � Substantially extending the roadmap beyond CMOS: � � New nano scale materials, devices New nano scale materials, devices • Near term: heterogeneous integration with CMOS • Near term: heterogeneous integration with CMOS • Long term: nano architectures • Long term: nano architectures
Nanoelectronic device candidates � Micro electronic devices � nano electronic devices � New means of processing / representing / storing information � New means of processing / representing / storing information � Nano system innovations � Nano system innovations � Emerging technologies � SET device � QCA device � Molecular device � Spin device � RTD device Carbon Nanotube (CNT) Three-terminal devices Array of cells with two Utilize bi-stable operation Two terminal devices with Three-terminal devices Resonant Tunneling Devices (RTD) modulate current through polarization states, of molecules with electron negative differential based on Coulomb spin coupling effects transport interacting with neighbors blockade resistance in I-V curve Single Electron Transistor (SET) � Identity of individual � High speed � Low power consumption through Coulomb Quantum Cellular Automata (QCA) In early research stage repulsions � Support quantum � Density � Density switches on sub-nm level Molecular Electronics (Molecular) � Morphological simplicity � Self-assembly capability computation Spin transistor (Spin) � Background charge � Standby power � Simple majority gate � Short coherence time � Difficulties in attaching fluctuations � Sensitivity to the � Sensitive to background electrical connections to � Promising device candidates � No viable device � Cryogenic operations thickness of tunneling well charge molecules demonstrated � Integration introduces � Logic & Memory � Cryogenic operations large delay
Nano devices: fundamental differences � Different means of physical basis Info storage mechanism: – Capacitor charge, interlocked state of logic gate vs. charge on floating gate, gate insulator, magnetization, etc State variables: – Voltage level vs. molecular state, spin orientation, phase state, etc Logic device: – 3 terminal FET vs. 1D structure, 2 terminal transistor, etc � Implication on logic gates / architecture � New basic logic gates Majority gate, XOR gate, Multi-Valued logic, … � � New supported logic architectures Crossbar, Cellular nonlinear network (CNN), bio-inspired neuro- � functions, …
Nano– O pportunities vs Challenges � advantages � Abundant HW resources � High speed � Challenges � Low power � Reliability – Defect – Transient fault � Interconnect – Nano-nano – Nano-CMOS � Fabrication – Bottom-up vs. top-down
F abrication & interconnect challenges • Fabrication � Fabrication implications: � � Fabrication implications: Traditional Top-down lithography fabrication � � Lead to Lead to large # of defects large # of defects reaching physical limits � � Result in Result in regular structures regular structures � Loss of accuracy � Require � Require reconfigurability reconfigurability � Expensive � � build arbitrary circuits build arbitrary circuits � Bottom-up fabrication � � bypass defects bypass defects � Self-assembly process • I nterconnect � Geometrical challenge of � Interconnect limitation: � Interconnect limitation: accessing nano scale devices � Localized interconnect � Localized interconnect Speed • � Expensive global � Expensive global Bandwidth • communications communications
Unreliability challenge � Extremely small scale � unreliability of nano devices � Expected behavior � Fabrication limitation: � random location / orientation of Permanent defects from nanotubes / nanowire growth manufacturing phase � Low noise / error immunity In-service occurring defects � stray charge influence � random charge hopping, crosstalk Semi-permanent errors � Single Event Upsets Transient errors � cosmic rays, noise, temperature fluctuations, … � Two forms of reliability challenges Manufacturing defects: offline detect & repair Dynamic fault occurrences: online fault tolerance
Specifically: new characteristics � Device density boost � Resource & redundancy exploitable � Supporting novel FT strategies � Novel basic gates � Reducing complexity involved in � Regularity of layout diagnosis � Flexibility � Reconfigurability � Topology concern � Interconnect limitations Interconnect High speed Nanoelectronic Unreliability Regular Structure environment High density New gates Reconfigurability
Hierarchical system construction ? ? � The only way to approach System complex systems � Mature methodologies for Computational ? ? current CMOS systems component � CMOS � nano: complexity � � New challenge Basic gate ? ? � Drastic device change � New design optimization considerations Interconnect High speed Unreliability High density Nano-scale Regular Structure New gates devices Reconfigurability
R eliable nano system construction FT Design hierarchy Nano approaches level characteristics • High level – processor � High / variable / � Time • Complex component clustering fault rate � Complex control for redundancy powerful strategies � Interconnect constraint � Info • Mid level – Arithmetic Regular structure � � Data transfer redundancy � Computation Novel logic gates � Reconfigurability � � HW • Low level – logic gate Abundant HW redundancy � • Simple unit � Simple strategy with low control overhead
Hierarchical F ault Tolerance � For clustered fault behavior Superscaling effects in nano � Can utilize various F.T. schemes System Applicable F.T. schemes vary at different levels � Hierarchical F.T. Arithmetic � High fault rates – faults filtered through levels � Clustering of faults – upper Logic level can use more global resources � Variable fault rates – flexible Device
Hierarchical F T in Nano system � Processor architecture Processor architecture � FT computational model – HW, performance, F.T. capability Topology consideration – Distributed control � Arithm etic com ponent Arithm etic com ponent � Memory / data transfer – Coding based FT C C Arithmetic / logic computation unit C V – NMR based fault masking – Reconfiguration based online repair � Logic gate Logic gate � Defect aware logic synthesis HW redundancy based FT
Nano system: order out of disorder � Reliability � Goal: reliable computation � Challenge: unreliable HW � Feasibility: given enough redundancy – von Neumann von Neumann : computations may be done reliably with a high – probability, even based on gates with certain failure probability – given enough HW redundancy. � Nanoelectronic systems � Goal: extending Moore’s law beyond CMOS scale � Foreseeable severe challenges � Eventually deliverable – given the involvement of active research
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