MPSoC 2006 TM tech DaVi Vinci nci TM chno nolo logy gy fo for - PDF document

MPSoC 2006 TM tech DaVi Vinci nci TM chno nolo logy gy fo for di digi gital tal vi vide deo ap o appl plicati cations ns Deepu Talla, Ph.D. System Architect 1 Overview DaVinci TM technology overview • DM644x SoC architecture • Software platform overview • Video performance • Power management • 2 1

Digital media SoC platform Flexibility for Innovation FPGA DSP CPU ASSP ASIC Integration-Level 3 Complete offering to enable digital video innovation Processors: Digital video system-on-chips – TMS320DM6443 – Video decode DM644x – TMS320DM6446 – Video encode/decode Software: Open, optimized and production tested – Platform-optimized, multimedia codecs – Industry-recognized APIs – Platform support package – Multimedia frameworks – Linux support package Tools: Validated software and hardware development DVEVM Digital Video Evaluation Module 4 2

Video chip evolution Digital Media SOC Digital Media Processor Video-capable DSP DaVinci™ Video-Imaging Video Processing Subsystem TMS320C6414 TMS320DM642 Coprocessor (VICP) Video Front End EMIF 64 ARM DSP Resizer port-0 Subsystem Subsystem CCD Controller Histogram/3A EMIF 16 Video Interface Preview L1P Cache L1P Cache L2 Cache/Memory 256 KBytes Video Video Processing Subsystem L2 Cache/Memory 1M Bytes Enhanced DMA Controller Enhanced DMA Controller C64x+ TM DSP 16 KBytes McBSP 0 16 KBytes ARM926EJ-S port-1 Back End 300 MHz 600 MHz On-Screen Video 10b DAC McBSP 1 CPU Core Video 10b DAC Display Enc 10b DAC port-2 (OSD) (VENC) McBSP 2 10b DAC C64x TM C64x TM 8-bit McASP HPI32 Switched Central Resource (SCR) DSP Core DSP Core 2 McBSPs Peripherals Connectivity System 10/100 USB Ethernet MAC EMAC EDMA General- Watchdog 2.0 VLYNQ With PWM Purpose Timer PWM L1D Cache L1D Cache MDIO PHY PWM 32-bit HPI Timer 16 KBytes 16 KBytes Serial Interfaces Program/Data Storage 66 MHz PCI Audio DDR2 ATA/ Async EMIF/ Serial I 2 C SPI UART MMC/ EMIF UART Controller NAND/ Compact Port UART SD SmartMedia (16b/32b) Flash 2001 2003 2005 5 TMS320DM644x block diagram Quality Multi-Format Video Encode/Decode Support • 600 MHz C64x+ DSP • Video Accelerators • High Bandwidth DDR2 Memory DSP Interface ARM9 ARM9 • Integrated Video Output 600-MHz 300-MHz System Integration & Flexibility Core CPU L2 SRAM 64kB Prog • 300 MHz ARM Host Processor 16kB I$, 8kB D$ L1 SRAM 32kB Prog • Programmable for Changing 16kB SRAM, ROM 80kB Data Standards System Connectivity • Ethernet MAC for Streaming Video • USB 2.0 for Consumer Peripherals Video Storage • ATA HDD interface • True IDE Compact Flash Interface Dedicated Video Processing Sub-system • Front end – Resizer, Image processing engine, 16-bit digital input 6 3

Video Optimized C64x+ ™ DSP DM644x™ Feature Benefit 32 KB L1P � Video Optimized DSP Video Cache/SRAM � Video 256 � H.264 MP D1 Decoding C64x+ Program Memory Megamodule Acceleration � VC-1/WMV9 D1 Decoding 64K Cache/SRAM Controller (PMC) Video Unified Memory Bandwidth Mgmt. Acceleration � 32kB L1P Cache/ � MPEG-2 MP@ML D1 Decoding 256 Controller Memory Protection 128 (UMC) 256 256 SRAM � MPEG-4 ASP D1 Decoding Bandwidth C64x+ Instruction Fetch Mgmt. 256 � 80kB L1D SRAM IDMA � H.264 BP D1 Encoding CPU SPLOOP Buffer Memory 16/32-bit Instruction Dispatch Protection � Simultaneous H.264 BP CIF Enc/Dec Instruction Decode • Up to 32kB Data Path 1 Data Path 2 128 M1 M2 External Audio (Concurrent with Video) L1 S1 xx D1 D2 xx S2 L2 Cache Memory xx xx Controller � 64kB L2 256 � MPEG-4 AAC LC and HE (EMC) A Register File B Register File DMA Slave 128 � MP3 I/F 64 Cache/SRAM Interrupt Data Memory Controller Master Port & Exception (DMC) Controller � 600 MHz � MPEG-1 Layer 1&2 128 256 (CPU/ cache Memory Protection req.) Power Bandwidth Mgmt. Control Security 32 � 128-Bit AES Decryption 80 KB L1D Cache/SRAM � Microsoft DRM Support Memory ARM � Programmability � Multi-Format Video Capability VPSS I/F Subsystem � Future Proof – Easily Upgradeable Switched Central Resource � C64x+ CPU � 100% Code Compatible from C64x™ � SPLOOP Buffer C64x+™ � Greater than 20% Code Size Advanced Serial Connec- DSP I/F Reduction � 16-Bit Instruction tivity Coding DM644x 7 ARM host DM644x ™ Feature Benefit Memory ARM VPSS � ARM9 Host � Standard OS Environment I/F Subsystem Processor � Flexible Network Protocol � 300 MHz Options Switched Central Resource � Simplifies User Interface � System Control Flexibility Advanced C64x+ Serial Connectivity DSP I/F � Efficient Application � Memory Execution DM644x � 8kB Data Cache � 16kB Instruction Cache � ARM Interrupt Cntl. 16kB RAM ARM926EJ - S D-cache I-cache 8KB 16KB RAM 16KB Boot ROM ARM Subsystem 8 4

Video processing sub system Composite & S-Video, or Composite & Component (YPbPr), DM644x Feature Benefit or SCART (Composite + RGB) � Integrated Video Output � Optimized Video System OSD OSD Cost � Video Video RGB888 @ 75 MHz Resizer Resizer Out Out � Standard Encoder � BTU656 : 8 or 16 bit @ 75 MHz Connectivity � Histogram Histogram Support for Standard LCD I/F Video Video /H3A /H3A In In � 4 10-bit 54MHz DACs Preview en Preview en � Integrated Display Driver � Composite VPSS VPSS � Multi-Format Support � S-Video � Optimized Video System � Component: RGB, YPbPr � Cost NTSC/PAL: 480/576 Interlaced � NTSC/PAL: 480/576 Progressive � Analog Codec Connectivity � Integrated Video Input Memory ARM VPSS � Digital Video Interface � I/F Subsystem CCD/CMOS Interface � Glueless Camera Interface • 16 bit at 75 MHz � BTU601/656 Interface � Video Format Flexibility Switched Central Resource • 8 or 16 bit at 75 MHz � Color Space Conversion C64x+™ Advanced Serial � Preview en Connec- DSP I/F � Off loads the DSP tivity � Bayer RGB to YCbCr 4:2:2 color � Programmable noise filter space conversion DM644x 9 Video processing sub system (continued) Composite & S-Video, or DM644x Feature Benefit Composite & Component (YPbPr), or SCART (Composite + RGB) � On Screen Display (OSD) � Picture in Picture � Video Window Capability OSD OSD Video Video • RGB888 � Easy to Use Attribute Resizer Resizer Out Out • YCbCr 4:2:2 Window Histogram Histogram � One OSD Bitmap Window Video Video � On Screen Application /H3A /H3A In In • RGB656 Control Previewer Previewer • One Attribute Window VPSS VPSS • 8 levels of blending � Resizer � Automatic Video � 4x to 1/4x Resizing Rescale • N/256 Zoom step � Offload CPU Processing � Linear and Bi-Cubic Resize Algorithm Memory ARM � Histogram/H3A VPSS Subsystem I/F � Automatic Focus � Statistical Engine for Calculating Control Exposure, White Balance, and Switched Central Resource Focus � Automatic White � Histogram data collection Balance Correction � Statistics collected in RGB Color Advanced C64x+™ Serial Space � Automatic Exposure Connec- DSP I/F � ARM and/or DSP can use these Compensation tivity statistics to control camera functions DM644x 10 5

Memory and storage interfaces DM644x ™ Feature Benefit DDR2-32b � DDR2-333 � Quality Video � 32-Bit Interface Processing � Up to 256MB MMC/SD � Advanced Codec � 166 MHz Clock Capability ATA/CF � Hard Disk Interface OR � Local Video Storage � ATA/ATAPI-5 HDD Interface AEMIF-16b � True IDE Compact Flash � Shared with EMIF � EMIF � Easy Boot � 4 Chip Selects Configuration Memory ARM � NAND Flash Connection VPSS I/F Subsystem � Expansion Capability • 2 x 8/16-bit NAND Devices Switched Central Resource • SM/xD � Asynchronous Memory Advanced C64x+™ Serial � Shared with ATA DSP Connect- I/F ivity � MultiMedia Card � MMC/SD Interface DM644x 11 Advanced connectivity DM644x ™ Feature Benefit Memory ARM VPSS I/F Subsystem � Ethernet MAC � Real-Time Streaming Video � 10/100 Mb/s � Integration Optimizes Cost Switched Central Resource � MII to Switch or PHY � MDIO Interface Advanced C64x+™ Serial Connec- DSP I/F tivity � Standard Expansion � USB 2.0 Interface � LNK + PHY DM644x � � High-speed Video Uploads High Speed (480Mps) � Host or client � VLYNQ ™ � FPGA Interface � EMAC 75 MHz Serial Connection � 802.11 WLAN Interface � 4 Serial Receive Pins � 4 Serial Transmit Pins USB 2.0 VLYNQ™ 12 6