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Motivation STM Best performance Faster Expected gains - PowerPoint PPT Presentation

F AST L ANE Streamlining Transactions for Low Thread Counts Jons-Tobias Wamhoff Christof Fetzer Technische Universitt Dresden, Germany Pascal Felber Etienne Rivire Universit de Neuchtel, Switzerland Gilles Muller INRIA, France


  1. F AST L ANE Streamlining Transactions for Low Thread Counts Jons-Tobias Wamhoff Christof Fetzer Technische Universität Dresden, Germany Pascal Felber Etienne Rivière Université de Neuchâtel, Switzerland Gilles Muller INRIA, France

  2. Motivation STM Best performance Faster Expected gains Performance from FastLane FastLane Sequential Slower x 1 Many Number of cores 2

  3. General Idea • 1 master thread • Commits transactions without aborting • Minimal instrumentation and bookkeeping • N helper threads • Commit transactions only when not in conflict • Contribute progress without impairing on the performance of the master 3

  4. Code Paths pessimistic speculative START code paths code paths SEQUENTIAL MASTER HELPER STM lightweight instrumented, instrumented, uninstru- instrumented synchronize extensive mented writes with master bookkeeping COMMIT 4

  5. Code Paths • Dresden TM Compiler • Generates multiple code paths for sequential (uninstrumented), FastLane (master & helper) and STM Generic START and COMMIT calls with internal branch • READ and WRITE are specific to code path and inlined • • transaction descriptor only accessed if needed • TinySTM++ TM runtime • Dynamically select code path based on core or thread count at BEGIN Christie et al.: Evaluation of AMD's Advanced Synchronization Facility Within a Complete Transactional Memory Stack, EuroSys '10 5

  6. Data Structures Memory Dirty array Master thread Counter ... odd: owned even: otherwise isMaster Address written Timestamp Helper thread Timestamp Address read ... Start timestamp Write-set Address read Read-set ... ... 6

  7. Master vs. Helper MASTER HELPER BEGIN BEGIN acquire( cntr ) start = cntr READ (addr) READ (addr) abort return *addr dirty [hash(addr)] ≤ start add(read-set, addr) WRITE (addr, val) return *addr dirty [hash(addr)] = cntr addr = val WRITE (addr, val) abort dirty [hash(addr)] ≤ start COMMIT put(write-set, addr, val) release( cntr ) COMMIT 7

  8. 3 Commit Variants COMMIT 1 acquire( cntr ) abort VALIDATE proceed 8

  9. 3 Commit Variants COMMIT 1 COMMIT 2 c = awaitEven( cntr ) acquire( cntr ) abort abort VALIDATE VALIDATE proceed acquire( cntr ) cntr ≤ c+1 ∨ abort VALIDATE proceed 8

  10. 3 Commit Variants COMMIT 1 COMMIT 2 COMMIT 3 c = awaitEven( cntr ) c = awaitEven( cntr ) acquire( cntr ) abort abort abort VALIDATE VALIDATE VALIDATE proceed acquire( cntr ) failed tryAcquire ( cntr , c) cntr ≤ c+1 ∨ abort proceed VALIDATE proceed Spear et al.: RingSTM: Scalable Transactions with a Single Atomic Instruction, SPAA '08 8

  11. Intset Benchmarks 9

  12. Thank you! 10

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