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More Than Just eFlash A Roadmap of How MRAM Will Change SoC - PowerPoint PPT Presentation

Nov 23, 2022 •6 likes •76 views

More Than Just eFlash A Roadmap of How MRAM Will Change SoC Architectures Introduction For many years, MRAM has been right around the corner. Bitline Its been billed as: SRAM killer eFlash replacement Enabler of instant on

  1. More Than Just eFlash A Roadmap of How MRAM Will Change SoC Architectures

  2. Introduction • For many years, MRAM has been “right around the corner.” Bitline Its been billed as:  SRAM killer  eFlash replacement  Enabler of instant on computers • At least 3 major foundries are preparing to bring eMRAM into production  Production expected by end of 2018  Currently 28nm/22nm; roadmaps for 14FF/12FF and below Sourceline • So how exactly will MRAM fit into SoC architecture initially and as the technology continues to evolve? Numem Confidential and Proprietary Information..

  3. Comparison Overview • Speed typically 10-100x faster than eFlash while SRAM MRAM eFlash still 2-10x slower than SRAM Read Time <1-2ns 2.0-20ns 10-100ns • Active power typically 10-50x lower than eFlash Write Time <1-2ns 10-1,000ns 10us-10ms  2-4x higher than SRAM for Read 0.1-0.4 0.2-2.0 uA/ 1-100 Read Power  4-200x higher than SRAM for Write uA/MHz/b MHz/b uA/MHz/b • Standby power near zero 0.5-2.0 2.0-400 100-2000 uA/ Write Power uA/MHz/b uA/MHz/b MHz/b  No bitcell current unlike SRAM  Core voltage only reads unlike eFlash Stdby Power High Low Med / Low Process Cost Baseline 5-10% 15-25% • Significantly lower cost than either memory  ~½ the area of SRAM 6T + low 2T + mid 2T-10T + high Area  Lower wafer cost and as much as 5x smaller than overhead overhead overhead eFlash Numem Confidential and Proprietary Information..

  4. Cost Advantages: Displacing eFlash • Preliminary driver of change is cost MRAM MRAM  15-20% cost reduction expected (within scaling Core CPU Logic Core CPU Logic Core CPU Logic (Data) (Data) eFlash (Data) trend) > ~10% wafer cost reduction due to larger geometry, L1 Cache L1 Cache L1 Cache backend layers L2 Cache L2 Cache L2 Cache MRAM MRAM > ~5-10% die size reduction, depending on ratio of die (S&D) (S&D) eFlash SRAM SRAM SRAM spent on eFlash / MRAM (S&D) (S&D) (S&D) (S&D) L3 Cache L3 Cache L3 Cache SPI SPI SPI IO’s / Analog IO’s / Analog IO’s / Analog • Reduced cost/bit will shift boundary for internal / external NVM usage  Power savings  Board route reductions SPI Flash SPI Flash SPI Flash  Fewer pass-through costs Numem Confidential and Proprietary Information..

  5. Performance Implications: MRAM v SRAM • Store&Download Schemes Unnecessary  2-4x Speed / Power of SRAM with no idle power MRAM MRAM MRAM MRAM MRAM MRAM  Savings can enable larger XIP area Core CPU Logic Core CPU Logic Core CPU Logic Core CPU Logic Core CPU Logic Core CPU Logic (Data) (Data) (Data) (Data) (Data) (Data) • L3 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache  Bit-Alterable design enables SRAM-type usage  No idle power L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache MRAM MRAM MRAM MRAM MRAM MRAM  Area / Power savings can enable larger cache (S&D) (XIP) (XIP) (XIP) (XIP) (XIP) SRAM L3 Cache (MRAM) L3 Cache (MRAM) L3 Cache (MRAM) (S&D) L3 Cache L3 Cache L3 Cache • L2 Cache  IoT and other power sensitive applications will benefit SPI SPI SPI SPI SPI SPI IO’s / Analog IO’s / Analog IO’s / Analog IO’s / Analog IO’s / Analog IO’s / Analog  Performance differences will make this a tougher boundary to cross • L1 Cache / Main SRAM  Low duty cycle applications (e.g. remote sensors)  “Instant On” valued over performance; NVM nature preserves state of cache SPI Flash SPI Flash SPI Flash SPI Flash SPI Flash SPI Flash when off  Limited application expected Numem Confidential and Proprietary Information..

  6. Technology Availability • eFlash has run ~3 technology generations behind logic 40nm  While some announcements have been made for 28nm eFlash, most foundries 28nm indicate that 40nm will be the last node 20nm 14nm • MRAM will intersect on this same trend line, but accelerate from there 10nm  2 nd generation MRAM should shave 2-3 7nm years off this trend Logic Process  3 rd generation MRAM should be just 1 year behind the logic process eFlash Process MRAM Process Numem Confidential and Proprietary Information..

  7. Closing • 2018 will see the first broad availability of MRAM from major foundries • Whether your priorities are cost, performance, or time to market, MRAM can enhance any SoC architecture • Numem is ready to help companies lead in MRAM deployment  Over 45 years of experience in MRAM design  Leading edge density, performance, and power  Focus on helping customers bring their products to market Numem Confidential and Proprietary Information..

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